Inventor

Shinichi Tanimoto

Inventor

Kyoto, JP

Overview

18→

Patents

1978–2011

Patent span

Electricity

Primary field (CPC H)

Patents· 18 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H05Kprimary

H05KPrinted circuits19%

G06FElectric digital data processing16%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%

H04BTransmission11%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%

H04LTransmission of digital information, e.g. telegraphic communication8%

A23PShaping or working of foodstuffs, not fully covered by a single other subclass3%

B29CShaping or joining of plastics3%

B29KIndexing scheme associated with subclasses b29b, b29c or b29d, relating to moulding materials or to materials for moulds, reinforcements, fillers or preformed parts, e.g. inserts3%

C08LCompositions of macromolecular compounds3%

PatentTitleYear

8,027,391'Differential transmission line connector'2011 7,781,677'Transmission cable'2010 7,741,876'Differential transmission line'2010 7,397,322'Radiation noise suppression circuit for differential transmission line'2008 7,388,449'Radiation noise suppression circuit for differential transmission line'2008 7,257,792'Wiring board design aiding apparatus, design aiding method, storage medium, and computer program'2007 7,120,885'Computer aided design apparatus for aiding design of a printed wiring board to effectively reduce noise'2006 7,117,459'Layout check system'2006 6,901,343'MULTILAYER BOARD IN WHICH WIRING OF SIGNAL LINE THAT REQUIRES TAMPER-RESISTANCE IS COVERED BY COMPONENT OR FOIL, DESIGN APPARATUS, METHOD, AND PROGRAM FOR THE MULTILAYER BOARD, AND MEDIUM RECORDING THE PROGRAM'2005 6,794,283'Semiconductor device and fabrication method thereof'2004 6,631,509'Computer aided design apparatus for aiding design of a printed wiring board to effectively reduce noise'2003 6,629,302'Circuit board design aiding apparatus, design aiding method, and storage medium storing design aiding program'2003 6,380,064'Semiconductor devices and process for producing the same'2002 6,342,440'Method for forming low-leakage impurity regions by sequence of high-and low-temperature treatments'2002 5,898,221'Semiconductor device having upper and lower wiring layers'1999 5,895,265'Semiconductor device having cap-metal layer'1999 5,635,763'Semiconductor device having cap-metal layer'1997 4,076,846'Protein-starch binary molding composition and shaped articles obtained therefor'1978

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1978Patents assigned to SUMITOMO BAKELITE CO (1)· patent assignee history

1997–2004Patents assigned to SANYO ELECTRIC CO (6)· patent assignee history

1997–1999Based in Ohgaki, JP· patent location history

1999–2004Based in Bisai, JP· patent location history

2003–2008Patents assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO LTD (7)· patent assignee history

2003–2006Based in Neyagawa, JP· patent location history

2005–2007Based in Katano, JP· patent location history

2008–2011Based in Kyoto, JP· patent location history

2010–2011Patents assigned to PANASONIC CORP (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MATSUSHITA ELECTRIC INDUSTRIAL CO LTD	7	2003–2008
SANYO ELECTRIC CO	6	1997–2004
PANASONIC CORP	3	2010–2011
SUMITOMO BAKELITE CO	1	1978

Locations

Location	Patents	Span
Kyoto, JP	5	2008–2011
Bisai, JP	4	1999–2004
Neyagawa, JP	3	2003–2006
Katano, JP	2	2005–2007
Ohgaki, JP	2	1997–1999