Inventor

Albert Wu

Inventor

Palo Alto, CA, US

Overview

1988–2017

Patent span

Electricity

Primary field (CPC H)

Patents· 107 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1024%

G11CStatic stores13%

H01LSemiconductor devices13%

H10BElectronic memory devices12%

H10DInorganic electric semiconductor devices8%

G06FElectric digital data processing6%

H10NElectric solid-state devices not otherwise provided for6%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%

Y10TTechnical subjects covered by former us classification3%

G01RMeasuring electric variables1%

PatentTitleYear

9,768,144'Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate'2017 9,659,851'Method and apparatus for improving the reliability of a connection to a via in a substrate'2017 9,565,770'Methods of making packages using thin Cu foil supported by carrier Cu foil'2017 9,490,427'Resistive random access memory cell structure'2016 9,444,510'Method and apparatus for incorporating passive devices in an integrated passive device separate from a die'2016 9,391,045'Recessed semiconductor substrates and associated techniques'2016 9,368,433'Method and apparatus for mounting solder balls to an exposed pad or terminal of a semiconductor package'2016 9,275,929'Package assembly having a semiconductor substrate'2016 9,275,731'Systems and methods for increasing the read sensitivity of a resistive random access memory (RRAM)'2016 9,257,410'Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate'2016 9,245,961'Reducing source contact to gate spacing to decrease transistor pitch'2016 9,244,115'Test engine for integrated circuit chip testing'2016 9,214,230'Resistive random access memory cell structure with reduced programming voltage'2015 9,171,744'Attaching passive components to a semiconductor package'2015 9,147,837'Resistive memory cell and method for forming a resistive memory cell'2015 9,142,445'Method and apparatus for forming shallow trench isolation structures having rounded corners'2015 9,129,678'Method and apparatus for reforming a memory cell of a memory'2015 9,117,734'Integrated circuit architecture for light emitting diode-based displays'2015 9,112,133'Resistive random access memory and method for controlling manufacturing of corresponding sub-resolution features of conductive and resistive elements'2015 9,099,335'Analog circuit with improved layout for mismatch optimization'2015 9,087,835'Structures embedded within core material and methods of manufacturing thereof'2015 9,070,679'Semiconductor package with a semiconductor die embedded within substrates'2015 9,064,860'Method for forming one or more vias through a semiconductor substrate and forming a redistribution layer on the semiconductor substrate'2015 9,047,945'Systems and methods for reading resistive random access memory (RRAM) cells'2015 9,047,252'Method and apparatus for detecting a row or a column of a memory to repair without reporting all corresponding defective memory cells'2015 9,042,159'Configuring resistive random access memory (RRAM) array for write operations'2015 9,034,730'Recessed semiconductor substrates and associated techniques'2015 8,999,786'Reducing source contact to gate spacing to decrease transistor pitch'2015 8,987,893'Heat dissipating interposers'2015 8,987,830'Attaching passive components to a semiconductor package'2015 8,946,890'Power/ground layout for chips'2015 8,947,909'System and method for creating a bipolar resistive RAM (RRAM)'2015 8,934,285'Method and apparatus for forming a contact in a cell of a resistive random access memory to reduce a voltage required to program the cell'2015 8,885,388'Apparatus and method for reforming resistive memory cells'2014 8,884,419'Integrated circuit packaging configurations'2014 8,873,309'Apparatus and method for repairing resistive memories and increasing overall read sensitivity of sense amplifiers'2014 8,861,214'High resistivity substrate for integrated passive device (IPD) applications'2014 8,796,839'Semiconductor package including a power plane and a ground plane'2014 8,767,491'Apparatus and method for remapping addresses of defective memory locations to redundant memory locations'2014 8,762,801'Method and system for detecting and repairing defective memory cells without reporting a defective memory cell'2014 8,753,976'Methods and apparatus for etching photo-resist material through multiple exposures of the photo-resist material'2014 8,754,506'Through via semiconductor die with backside redistribution layer'2014 8,748,910'Systems and methods for integrating LED displays and LED display controllers'2014 8,624,377'Method of stacking flip-chip on wire-bonded chip'2014 8,618,654'Structures embedded within core material and methods of manufacturing thereof'2013 8,609,528'High-density patterning'2013 8,603,861'Alpha shielding techniques and configurations'2013 8,518,742'Semiconductor packaging with internal wiring bus'2013 8,501,619'Methods for forming a plurality of contact holes in a microelectronic device'2013 8,471,376'Integrated circuit packaging configurations'2013 8,462,569'Memory repair system and method'2013 8,423,841'Method and systems for memory testing and test data reporting during memory testing'2013 8,372,692'Method of stacking flip-chip on wire-bonded chip'2013 8,368,214'Alpha shielding techniques and configurations'2013 8,338,934'Embedded die with protective interposer'2012 8,330,477'Test engine for integrated circuit chip testing'2012 8,319,353'Pre-formed conductive bumps on bonding pads'2012 8,241,993'Method for shallow trench isolation'2012 8,218,383'Memory repair system and method'2012 8,030,098'Pre-formed conductive bumps on bonding pads'2011 8,030,128'Method to form high density phase change memory (PCM) top contact every two bits'2011 8,008,137'Method for fabricating 1T-DRAM on bulk silicon'2011 8,003,523'Methods for forming a plurality of contact holes in a microelectric device'2011 7,994,052'High-density patterning'2011 7,985,616'Methods to form wide heater trenches and to form memory cells to engage heaters'2011 7,960,831'Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same'2011 7,958,413'Method and system for memory testing and test data reporting during memory testing'2011 7,948,818'Memory repair system and method'2011 7,939,445'High density via and metal interconnect structures, and methods of forming the same'2011 7,939,414'Ion implantation and process sequence to form smaller base pick-up'2011 7,911,053'Semiconductor packaging with internal wiring bus'2011 7,892,936'Self aligned integration of high density phase change memory with thin film access device'2011 7,888,166'Method to form high efficiency GST cell using a double heater cut'2011 7,863,709'Low base resistance bipolar junction transistor array'2011 7,834,341'Phase change material (PCM) memory devices with bipolar junction transistors and methods for making thereof'2010 7,825,521'Stack die packages'2010 7,820,493'Methods of making and using fuse structures, and integrated circuits including the same'2010 7,807,539'Ion implantation and process sequence to form smaller base pick-up'2010 7,751,264'Memory repair system and method'2010 7,745,809'Ultra high density phase change memory having improved emitter contacts, improved GST cell reliability and highly matched UHD GST cells using column mirco-trench strips'2010 7,734,966'Method and system for memory testing and test data reporting during memory testing'2010 7,709,835'Method to form high efficiency GST cell using a double heater cut'2010 7,704,805'Fuse structures, methods of making and using the same, and integrated circuits including the same'2010 7,704,875'High-density contact holes'2010 7,694,440'Insole cushioning device with repelling magnetic field'2010 7,622,731'Cross-point memory array'2009 7,589,363'Fuse structures, methods of making and using the same, and integrated circuits including the same'2009 7,535,110'Stack die packages'2009 7,359,261'Memory repair system and method'2008 7,344,924'Fuse structures, methods of making and using the same, and integrated circuits including the same'2008 7,314,819'Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same'2008 7,288,845'Fabrication of wire bond pads over underlying active devices, passive devices and/or dielectric layers in integrated circuits'2007 6,940,107'Fuse structures, methods of making and using the same, and integrated circuits including the same'2005 6,876,031'Method and apparatus for split gate source side injection flash memory cell and array with dedicated erase gates'2005 6,323,089'Semiconductor memory array with buried drain lines and processing methods therefor'2001 6,274,436'Method for forming minute openings in semiconductor devices'2001 6,211,547'Semiconductor memory array with buried drain lines and processing methods therefor'2001 6,102,339'Sun-synchronous sun ray blocking device for use in a spacecraft having a directionally controlled main body'2000 6,088,577'Multiple subcarrier communication system'2000 5,986,934'Semiconductor memory array with buried drain lines and methods therefor'1999 5,903,487'Memory device and method of operation'1999 5,881,365'Digital compressed voice paging system which uses R.D.S. format for the ID signals and S.C.A. format for the voice signals both formats being FM subcarriers'1999 5,453,388'Method of making an EEPROM'1995 5,373,465'Non-volatile semiconductor memory cell'1994 5,317,179'Non-volatile semiconductor memory cell'1994 5,256,594'Masking technique for depositing gallium arsenide on silicon'1993 4,794,565'Electrically programmable memory device employing source side injection'1988

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–1995Based in San Jose, CA, US· patent location history

1999–2017Based in Palo Alto, CA, US· patent location history

2000Based in Paramus, NJ, US· patent location history

2005–2016Patents assigned to MARVELL INT LTD (46)· patent assignee history

2008–2011Based in Taoyuan, TW· patent location history

2009–2017Patents assigned to MARVELL WORLD TRADE LTD (43)· patent assignee history

2010–2016Patents assigned to WU ALBERT (25)· patent assignee history

2010Based in San Marino, CA, US· patent location history

2012–2016Patents assigned to LIOU SHIANN-MING (9)· patent assignee history

2013–2016Patents assigned to WEI CHIEN-CHUAN (6)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MARVELL INT LTD	46	2005–2016
MARVELL WORLD TRADE LTD	43	2009–2017
WU ALBERTself	25	2010–2016
LIOU SHIANN-MING	9	2012–2016
WEI CHIEN-CHUAN	6	2013–2016

Locations

Location	Patents	Span
Palo Alto, California, US	96	1999–2017
San Jose, California, US	4	1993–1995
Taoyuan, TW	2	2008–2011
Paramus, New Jersey, US	2	2000
San Marino, California, US	1	2010