Inventor

Stephen P. Sample

Inventor

Saratoga, CA, US

Overview

43→

Patents

1978–2017

Patent span

Physics

Primary field (CPC G)

Patents· 43 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing37%

H03KPulse technique24%

G01RMeasuring electric variables10%

G11CStatic stores9%

H04LTransmission of digital information, e.g. telegraphic communication6%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%

H05KPrinted circuits4%

G05BControl or regulating systems in general1%

H01RElectrically-conductive connections1%

PatentTitleYear

9,645,951'Accelerator system for remote data storage'2017 9,411,524'Accelerator system for use with secure data storage'2016 8,824,492'Accelerator system for remote data storage'2014 8,601,498'Accelerator system for use with secure data storage'2013 7,856,546'Configurable processor module accelerator using a programmable logic device'2010 7,739,097'Emulation system with time-multiplexed interconnect'2010 6,882,176'High-performance programmable logic architecture'2005 6,842,729'Apparatus for emulation of electronic systems'2005 6,732,068'Memory circuit for use in hardware emulation system'2004 6,694,464'Method and apparatus for dynamically testing electrical interconnect'2004 6,625,793'Optimized emulation and prototyping architecture'2003 6,570,404'High-performance programmable logic architecture'2003 6,567,967'Method for designing large standard-cell base integrated circuits'2003 6,377,912'Emulation system with time-multiplexed interconnect'2002 6,377,911'Apparatus for emulation of electronic hardware system'2002 6,353,552'PLD with on-chip memory having a shadow register'2002 6,317,367'FPGA with on-chip multiport memory'2001 6,289,494'Optimized emulation and prototyping architecture'2001 6,285,211'I/O buffer circuit with pin multiplexing'2001 6,259,588'Input/output buffer with overcurrent protection circuit'2001 6,219,284'Programmable logic device with multi-port memory'2001 6,184,707'Look-up table based logic element with complete permutability of the inputs to the secondary signals'2001 6,151,258'Programmable logic device with multi-port memory'2000 6,058,492'Method and apparatus for design verification using emulation and simulation'2000 6,034,857'Input/output buffer with overcurrent protection circuit'2000 6,020,760'I/O buffer circuit with pin multiplexing'2000 6,011,744'Programmable logic device with multi-port memory'2000 6,011,730'Programmable logic device with multi-port memory'2000 5,963,735'Hardware logic emulation system'1999 5,960,191'Emulation system with time-multiplexed interconnect'1999 5,943,490'Distributed logic analyzer for use in a hardware logic emulation system'1999 5,887,158'Switching midplane and interconnecting system for interconnecting large numbers of signals'1999 5,870,410'Diagnostic interface system for programmable logic system development'1999 5,841,967'Method and apparatus for design verification using emulation and simulation'1998 5,821,773'Look-up table based logic element with complete permutability of the inputs to the secondary signals'1998 5,644,515'Hardware logic emulation system capable of probing internal nodes in a circuit design undergoing emulation'1997 5,477,475'Method for emulating a circuit design using an electrically reconfigurable hardware emulation apparatus'1995 5,452,239'Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system'1995 5,352,123'Switching midplane and interconnection system for interconnecting large numbers of signals'1994 5,329,470'Reconfigurable hardware emulation system'1994 5,114,353'Multiple connector arrangement for printed circuit board interconnection'1992 5,109,353'Apparatus for emulation of electronic hardware system'1992 4,099,236'Slave microprocessor for operation with a master microprocessor and a direct memory access controller'1978

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1978Based in Los Altos, CA, US· patent location history

1992–1994Patents assigned to QUICKTURN SYSTEMS INC (4)· patent assignee history

1992–2005Based in Mountain View, CA, US· patent location history

1995–2010Patents assigned to QUICKTURN DESIGN SYSTEMS INC (29)· patent assignee history

1998–2003Patents assigned to ALTERA CORP (14)· patent assignee history

1998–2017Based in Saratoga, CA, US· patent location history

2010–2014Patents assigned to DRC COMP CORP (2)· patent assignee history

2013–2014Patents assigned to CASSELMAN STEVEN MARK (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
QUICKTURN DESIGN SYSTEMS INC	29	1995–2010
ALTERA CORP	14	1998–2003
QUICKTURN SYSTEMS INC	4	1992–1994
CASSELMAN STEVEN MARK	2	2013–2014
DRC COMP CORP	2	2010–2014

Locations

Location	Patents	Span
Saratoga, California, US	31	1998–2017
Mountain View, California, US	11	1992–2005
Los Altos, California, US	1	1978