Inventor
Jerome F. Duluk, Jr.
Inventor
Palo Alto, CA, US
Overview
Patents· 123 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Tprimary
G06TImage data processing or generation, in general38%
G06FElectric digital data processing36%
G09GArrangements or circuits for control of indicating devices using static means to present variable information10%
H04NPictorial communication, e.g. television4%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%
G01RMeasuring electric variables2%
H05KPrinted circuits2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
B41FPrinting machines or presses1%
PatentTitleYear
10,915,364Technique for computational nested parallelism202110,817,338Dynamic partitioning of execution resources202010,795,722Compute task state encapsulation202010,445,243Fault buffer for resolving page faults in unified virtual memory system201910,438,314Two-pass cache tile processing for visibility testing in a tile-based architecture201910,409,730Microcontroller for memory management unit201910,331,603PCIe traffic tracking hardware in a unified virtual memory system201910,310,973Efficient memory virtualization in multi-threaded processing units201910,303,616Migration scheme for unified virtual memory system201910,223,122Managing event count reports in a tile-based architecture201910,216,413Migration of peer-mapped memory pages201910,217,183System, method, and computer program product for simultaneous execution of compute and graphics workloads201910,169,091Efficient memory virtualization in multi-threaded processing units201910,169,072Hardware for parallel command list generation201910,133,677Opportunistic migration of memory pages in a unified virtual memory system201810,114,758Techniques for supporting for demand paging201810,078,911System, method, and computer program product for executing processes involving at least one primitive in a graphics processor, utilizing a data structure201810,061,526Frame buffer access tracking via a sliding window in a unified virtual memory system201810,037,228Efficient memory virtualization in multi-threaded processing units201810,031,856Common pointers in unified virtual memory system20189,965,321Error checking in out-of-order task scheduling20189,953,455Handling post-Z coverage data in raster operations20189,952,868Two-pass cache tile processing for visibility testing in a tile-based architecture20189,940,286PCIE traffic tracking hardware in a unified virtual memory system20189,830,262Access tracking mechanism for hybrid memories in a unified virtual system20179,830,210CPU-to-GPU and GPU-to-GPU atomics20179,830,276Replaying memory transactions while resolving memory access faults20179,798,487'Migrating pages of different sizes between heterogeneous processors'20179,792,220'Microcontroller for memory management unit'20179,767,036'Page state directory for managing unified virtual memory'20179,754,561'Managing memory regions to support sparse mappings'20179,734,545'Software methods in a GPU'20179,715,413'Execution state analysis for assigning tasks to streaming multiprocessors'20179,710,306'Methods and apparatus for auto-throttling encapsulated compute tasks'20179,679,350'Techniques for optimizing stencil buffers'20179,639,474'Migration of peer-mapped memory pages'20179,639,367'Managing event count reports in a tile-based architecture'20179,612,839'Higher accuracy Z-culling in a tile-based architecture'20179,588,903'Microcontroller for memory management unit'20179,589,310'Methods to facilitate primitive batching'20179,575,892'Replaying memory transactions while resolving memory access faults'20179,513,975'Technique for computational nested parallelism'20169,507,638'Compute work distribution reference counters'20169,495,721'Efficient super-sampling with per-pixel shader threads'20169,442,759'Concurrent execution of independent streams in multi-channel time slice groups'20169,430,400'Migration directives in a unified virtual memory system architecture'20169,424,201'Migrating pages of different sizes between heterogeneous processors'20169,418,616'Technique for storing shared vertices'20169,401,004'State shadowing to support a multi-threaded driver environment'20169,396,515'Rendering using multiple render target sample masks'20169,378,139'System, method, and computer program product for low latency scheduling and launch of memory defined tasks'20169,355,430'Techniques for interleaving surfaces'20169,355,041'Frame buffer access tracking via a sliding window in a unified virtual memory system'20169,311,097'Managing per-tile event count reports in a tile-based architecture'20169,293,109'Technique for storing shared vertices'20169,275,491'GPU work creation and stateless graphics in OPENGL'20169,183,609'Programmable blending in multi-threaded processing units'20159,098,925'Techniques for optimizing stencil buffers'20159,098,924'Techniques for optimizing stencil buffers'20159,082,212'Programmable blending via multiple pixel shader dispatches'20159,069,609'Scheduling and execution of compute tasks'20159,013,498'Determining a working set of texture maps'20158,984,183'Signaling, ordering, and execution of dynamically generated tasks in a processing system'20158,970,608'State objects for specifying dynamic state'20158,922,555'Pixel shader output map'20148,860,743'Sparse texture systems and methods'20148,823,724'Sparse texture systems and methods'20148,786,618'Shader program headers'20148,766,988'Providing pipeline state through constant buffers'20148,760,455'Restart index that sets a topology'20148,749,562'Sharing binding groups between shaders'20148,681,169'Sparse texture systems and methods'20148,669,991'Method macro expander'20148,619,087'Inter-shader attribute buffer optimization'20138,525,842'System and method for utilizing semaphores in a graphics pipeline'20138,493,395'Hardware override of application programming interface programmed state'20138,427,493'Draw commands with built-in begin/end'20138,429,656'Thread count throttling for efficient resource utilization'20138,330,766'Zero-bandwidth clears'20128,319,783'Index-based zero-bandwidth clears'20128,228,338'Hardware override of application programming interface programmed state'20128,223,158'Method and system for connecting multiple shaders'20128,134,570'System and method for graphics attribute packing for pixel shader usage'20128,085,275'System and method for low-overhead push buffer jumps'20118,044,966'Method and apparatus for display image adjustment'20117,961,197'Method and apparatus for display image adjustment'20117,880,747'Blend optimizations that are conformant to floating-point rules'20117,808,503'Deferred shading graphics pipeline processor having advanced features'20107,791,614'Method and apparatus for display image adjustment'20107,739,556'Hardware override of application programming interface programmed state'20107,697,007'Predicated launching of compute thread arrays'20107,623,135'Method and apparatus for display image adjustment'20097,526,634'Counter-based delay of dependent thread group execution'20097,167,181'Deferred shading graphics pipeline processor having advanced features'20077,164,426'Method and apparatus for generating texture'20077,009,605'System, method and computer program product for generating a shader program'20066,771,264'Method and apparatus for performing tangent space lighting and bump mapping in a deferred shading graphics processor'20046,717,576'Deferred shading graphics pipeline processor having advanced features'20046,693,639'Graphics processor with pipeline state storage and retrieval'20046,671,747'System, apparatus, method, and computer program for execution-order preserving uncached write combine operation'20036,664,959'Method and apparatus for culling in a graphics processor with deferred shading'20036,614,444'Apparatus and method for fragment operations in a 3D-graphics pipeline'20036,597,363'Graphics processor with deferred shading'20036,577,305'Apparatus and method for performing setup operations in a 3-D graphics pipeline using unified primitive descriptors'20036,577,317'Apparatus and method for geometry operations in a 3D-graphics pipeline'20036,552,723'System, apparatus and method for spatially sorting image data in a three-dimensional graphics pipeline'2003RE038078'Graphical rendering system using simultaneous parallel query Z-buffer and method therefor'20036,525,737'Graphics processor with pipeline state storage and retrieval'20036,476,807'Method and apparatus for performing conservative hidden surface removal in a graphics processor with deferred shading'20026,288,730'Method and apparatus for generating texture'20016,285,378'Method and apparatus for span and subspan sorting rendering system'20016,268,875'Deferred shading graphics pipeline processor'20016,229,553'Deferred shading graphics pipeline processor'20016,166,554'Flexible electrical test fixture for integrated circuits on prototype and production printed circuit boards'20006,005,403'Flexible electrical test fixture for integrated circuits on prototype and production printed circuit boards'19995,977,987'Method and apparatus for span and subspan sorting rendering system'19995,692,911'Flexible electrical test fixure for integrated circuits on prototype and production printed circuit boards'19975,669,010'Cascaded two-stage computational SIMD engine having multi-port memory and multiple arithmetic units'19975,596,686'Method and apparatus for simultaneous parallel query graphics rendering Z-coordinate buffer'19975,574,835'Bounding box and projections detection of hidden polygons in three-dimensional spatial databases'19965,572,634'Method and apparatus for spatial simulation acceleration'19965,535,288'System and method for cross correlation with application to video motion vector estimator'19964,996,666'Content-addressable memory system capable of fully parallel magnitude comparisons'1991Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1991–2020Patents assigned to DULUK JR JEROME F (35)· patent assignee history
1991–2021Based in Palo Alto, CA, US· patent location history
1996–1997Based in Santa Clara, CA, US· patent location history
1996Based in Mountain View, CA, US· patent location history
2001–2007Patents assigned to APPLE COMPUTER (19)· patent assignee history
2006–2021Patents assigned to NVIDIA CORP (92)· patent assignee history
2012–2019Patents assigned to BROWN PATRICK R (9)· patent assignee history
2014–2019Patents assigned to HALL JESSE DAVID (9)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NVIDIA CORP | 92 | 2006–2021 |
| DULUK JR JEROME Fself | 35 | 1991–2020 |
| APPLE COMPUTER | 19 | 2001–2007 |
| BROWN PATRICK R | 9 | 2012–2019 |
| HALL JESSE DAVID | 9 | 2014–2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Palo Alto, California, US | 119 | 1991–2021 |
| Santa Clara, California, US | 3 | 1996–1997 |
| Mountain View, California, US | 1 | 1996 |