LexDanaLexDanabeta
Inventor

Michael A. Sorna

Inventor
Hopewell Junction, NY, US

Overview

56→
Patents
1992–2016
Patent span
Electricity
Primary field (CPC H)

Patents· 56 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H04Lprimary
H04LTransmission of digital information, e.g. telegraphic communication24%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses13%
G06FElectric digital data processing11%
G01RMeasuring electric variables10%
H03KPulse technique8%
G11CStatic stores6%
G05FSystems for regulating electric or magnetic variables5%
H03MCoding5%
H04BTransmission5%
H03FAmplifiers4%
PatentTitleYear
9,473,172'Receiver deserializer latency trim'20169,374,098'Transmitter serializer latency trim'20168,692,600'Multi-protocol driver slew rate calibration system for calibration slew rate control signal values'20148,674,737'Clock feathered slew rate control system'20148,543,753'Multi-use physical architecture'20138,493,801'Strobe offset in bidirectional memory strobe configurations'20138,493,117'Leakage tolerant delay locked loop circuit device'20138,410,835'Leakage tolerant phase locked loop circuit device'20138,401,135'Post-equalization amplitude latch-based channel characteristic measurement'20138,284,621'Strobe offset in bidirectional memory strobe configurations'20128,183,950'Auto-calibration for ring oscillator VCO'20128,183,949'Compensation of VCO gain curve offsets using auto-calibration'20128,144,726'Structure for out of band signaling enhancement for high speed serial driver'20128,130,887'Method and arrangements for link power reduction'20128,126,045'System and method for latency reduction in speculative decision feedback equalizers'20128,040,813'Apparatus and method for reduced loading of signal transmission elements'20118,024,679'Structure for apparatus for reduced loading of signal transmission elements'20117,974,304'Out of band signaling enhancement for high speed serial driver'20117,873,922'Structure for robust cable connectivity test receiver for high-speed data receiver'20117,869,544'System for measuring an eyewidth of a data signal in an asynchronous system'20117,855,563'Robust cable connectivity test receiver for high-speed data receiver'20107,840,916'Structure for on-chip electromigration monitoring system'20107,772,918'Regulated voltage boost charge pump for an integrated circuit device'20107,733,964'Automatic adaptive equalization method for high-speed serial transmission link'20107,719,302'On-chip electromigration monitoring'20107,680,179'Data communication system with self-test feature'20107,519,130'Front end interface for data receiver'20097,486,114'Signal detector with calibration circuit arrangement'20097,409,019'High Speed Multi-Mode Receiver with adaptive receiver equalization and controllable transmitter pre-distortion'20087,397,876'Methods and arrangements for link power reduction'20087,394,273'On-chip electromigration monitoring system'20087,394,283'CML to CMOS signal converter'20087,352,815'Data transceiver and method for equalizing the data eye of a differential input data signal'20087,321,617'Data communication system with self-test feature'20087,295,618'Automatic adaptive equalization method and system for high-speed serial transmission link'20077,142,623'On-chip system and method for measuring jitter tolerance of a clock and data recovery circuit'20067,132,821'Reference current generation system'20067,113,749'System and method for measuring a high speed signal'20067,102,392'Signal detector for high-speed serdes'20067,053,712'Method and apparatus for controlling common-mode output voltage in fully differential amplifiers'20066,980,824'Method and system for optimizing transmission and reception power levels in a communication system'20056,963,240'Damping of LC ringing in IC (integrated circuit) power distribution systems'20056,949,981'Dynamic threshold for VCO calibration'20056,937,054'Programmable peaking receiver and method'20056,891,357'Reference current generation system and method'20056,785,832'Process independent source synchronous data capture apparatus and method'20046,680,681'High speed FIR transmitter'20046,661,267'Coarse calibration circuit using variable step sizes to reduce jitter and a dynamic course calibration (DCC) circuit for a 2 GHz VCO'20036,528,777'Optical power meter derived from common-mode voltage of optical transimpedance amplifier'20036,466,100'Linear voltage controlled oscillator transconductor with gain compensation'20025,912,928'High speed serial data transmission encoder'19995,825,169'Dynamically biased current gain voltage regulator with low quiescent power consumption'19985,805,088'High speed asynchronous serial to parallel data converter'19985,661,395'Active, low Vsd, field effect transistor current source'19975,144,228'Probe interface assembly'19925,132,613'Low inductance side mount decoupling test structure'1992

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1992–2014Patents assigned to IBM (54)· patent assignee history
1992–1997Based in Poughkeepsie, NY, US· patent location history
1998–2016Based in Hopewell Junction, NY, US· patent location history
1998Based in Hopewell Jct., NY, US· patent location history
2011Based in Hopwell Junction, NY, US· patent location history
2012–2014Patents assigned to SORNA MICHAEL A (11)· patent assignee history
2012–2013Patents assigned to DREPS DANIEL M (3)· patent assignee history
2012–2013Patents assigned to KIM KYU-HYOUN (3)· patent assignee history
2012–2013Patents assigned to STORASKA DANIEL W (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM541992–2014
SORNA MICHAEL Aself112012–2014
DREPS DANIEL M32012–2013
KIM KYU-HYOUN32012–2013
STORASKA DANIEL W32012–2013
Locations
LocationPatentsSpan
Hopewell Junction, New York, US511998–2016
Poughkeepsie, New York, US31992–1997
Hopwell Junction, New York, US12011
Hopewell Jct., New York, US11998