Inventor
Daniel Boudreau
Inventor
Billerica, MA, US
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing39%
H04LTransmission of digital information, e.g. telegraphic communication39%
H04BTransmission13%
H04WWireless communication networks6%
G01RMeasuring electric variables3%
PatentTitleYear
9,125,061'Systems and methods for channel allocation for forward-link multi-user systems'20158,213,543'System and method for I/Q imbalance compensation'20128,045,936'Receiver for receiving embedding OFDM in an CDMA systems'20118,023,905'Method for embedding OFDM in CDMA systems'20117,869,538'System and method for I/Q imbalance compensation'20117,792,534'Multiple threshold scheduler'20107,486,735'Sub-carrier allocation for OFDM'20097,471,932'System and method for embedding OFDM in CDMA systems'20087,428,270'Method and system for detecting and classifying the modulation of unknown analog and digital telecommunications signals'20087,251,291'System and method for I/Q imbalance compensation'20077,177,371'Methods and apparatus for transmitting and receiving data over a communications network in the presence of interference'20076,788,692'Network switch load balancing'20044,949,340'Redundant repeater'19904,787,060'Technique for determining maximum physical memory present in a system and for detecting attempts to access nonexistent memory'19884,654,788'Asynchronous multiport parallel access memory system for use in a single board computer system'19874,600,992'Priority resolver with lowest priority level having shortest logic path'19864,587,609'Lockout operation among asynchronous accessers of a shared computer system resource'19864,563,736'Memory architecture for facilitating optimum replaceable unit (ORU) detection and diagnosis'19864,559,595'Distributed priority network logic for allowing a low priority unit to reside in a high priority position'19854,545,010'Memory identification apparatus and method'19854,511,960'Data processing system auto address development logic for multiword fetch'19854,503,495'Data processing system common bus utilization detection logic'19854,493,036'Priority resolver having dynamically adjustable priority levels'19854,453,093'Multiple comparison circuitry for providing a software error trace signal'1984Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1984–1987Patents assigned to HONEYWELL INF SYSTEMS (10)· patent assignee history
1984–1988Based in Billerica, MA, US· patent location history
1990–2004Based in Westford, MA, US· patent location history
2004–2011Patents assigned to NORTEL NETWORKS LTD (6)· patent assignee history
2007–2015Based in Hull, CA· patent location history
2008–2015Patents assigned to BOUDREAU DANIEL (3)· patent assignee history
2008–2012Patents assigned to DUBUC CHRISTIAN (2)· patent assignee history
2009Based in Gatineau, CA· patent location history
2010–2011Patents assigned to ERICSSON AB (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| HONEYWELL INF SYSTEMS | 10 | 1984–1987 |
| NORTEL NETWORKS LTD | 6 | 2004–2011 |
| BOUDREAU DANIELself | 3 | 2008–2015 |
| ERICSSON AB | 3 | 2010–2011 |
| DUBUC CHRISTIAN | 2 | 2008–2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Billerica, Massachusetts, US | 11 | 1984–1988 |
| Hull, CA | 10 | 2007–2015 |
| Westford, Massachusetts, US | 2 | 1990–2004 |
| Gatineau, CA | 1 | 2009 |