Inventor

Ssu-Pin Ma

Inventor
Taipei, TW

Overview

21→
Patents
1998–2015
Patent span
Electricity
Primary field (CPC H)

Patents· 21 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1022%
H10DInorganic electric semiconductor devices17%
H04BTransmission15%
G01RMeasuring electric variables5%
G02BOptical elements, systems or apparatus5%
H01FMagnets5%
H03FAmplifiers5%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
G05DSystems for controlling or regulating non-electric variables2%
G06FElectric digital data processing2%
PatentTitleYear
9,003,254'Methods and systems for testing electronic circuits'20158,737,545'Receiver chain gain selection'20148,694,845'Methods and systems for testing electronic circuits'20148,413,453'Auxiliary control device for air conditioning system'20138,180,304'Efficient power amplifier'20127,623,886'Method and apparatus for transmitter calibration'20097,437,139'Method and apparatus for calibrating filtering of a transceiver'20087,138,880'Turbo-charged relaxation oscillator method and apparatus'20067,038,294'Planar spiral inductor structure with patterned microelectronic structure integral thereto'20066,881,996'Metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer'20056,812,088'Method for making a new metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer'20046,667,217'Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process'20036,489,816'Frequency converter with direct current suppression'20026,472,721'Dual damascene interconnect structures that include radio frequency capacitors and inductors'20026,444,517'High Q inductor with Cu damascene via/trench etching simultaneous module'20026,404,030'Chain gate MOS structure'20026,366,764'Wireless transmitter/receiver utilizing DSSS technology'20026,329,234'Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow'20016,205,171'Antenna selector switch'20015,809,188'Tunable optical filter or reflector'19985,781,675'Method for preparing fiber-optic polarizer'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998Patents assigned to NAT SCIENCE COUNCIL (2)· patent assignee history
1998Based in Hsinchu, TW· patent location history
2001–2006Patents assigned to TAIWAN SEMICONDUCTOR MFG (8)· patent assignee history
2001–2002Patents assigned to IND TECH RES INST (2)· patent assignee history
2001–2006Based in Taipei, TW· patent location history
2002–2015Based in San Jose, CA, US· patent location history
2012–2015Patents assigned to MA SSU-PIN (5)· patent assignee history
2013Patents assigned to ARIPIRALA RAVI (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TAIWAN SEMICONDUCTOR MFG82001–2006
MA SSU-PINself52012–2015
IND TECH RES INST22001–2002
NAT SCIENCE COUNCIL21998
ARIPIRALA RAVI12013
Locations
LocationPatentsSpan
Taipei, TW112001–2006
San Jose, California, US82002–2015
Hsinchu, TW21998