Inventor
Mutsuo Morikado
Inventor
Yokohama, JP
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices39%
H10DInorganic electric semiconductor devices28%
G11CStatic stores14%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
PatentTitleYear
8,541,285'Semiconductor memory device and method for manufacturing the same'20138,492,825'Nonvolatile semiconductor memory device and method of fabricating the same'20138,369,152'Semiconductor memory device including charge accumulation layer'20138,362,543'Semiconductor nonvolatile memory device with inter-gate insulating film formed on the side surface of a memory cell and method for manufacturing the same'20138,358,537'Nonvolatile semiconductor memory device'20138,349,720'Nonvolatile semiconductor memory and manufacturing method thereof'20138,319,270'Semiconductor device and method for manufacturing the same'20128,238,159'Non-volatile semiconductor storage device and method of controlling the same'20128,154,069'NAND flash memory with selection transistor having two-layer inter-layer insulation film'20128,017,987'Semiconductor memory device and method for manufacturing the same'20118,013,382'NAND flash memory and method of manufacturing the same'20117,915,680'Semiconductor device and manufacturing method of the same'20117,750,404'Semiconductor device and method of manufacturing the same'20107,583,538'Semiconductor memory and read method of the same'20097,449,375'Fin semiconductor device and method for fabricating the same'20087,433,234'Floating-body cell (FBC) semiconductor storage device having a buried electrode serving as gate electrode, and a surface electrode serving as plate electrode'20087,145,220'Fin semiconductor device and method for fabricating the same'20066,479,368'Method of manufacturing a semiconductor device having a shallow trench isolating region'20025,866,946'Semiconductor device having a plug for diffusing hydrogen into a semiconductor substrate'19995,447,884'Shallow trench isolation with thin nitride liner'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2002Patents assigned to IBM (2)· patent assignee history
1999–2013Patents assigned to TOSHIBA KK (19)· patent assignee history
1999Based in Poughkeepsie, NY, US· patent location history
2002–2013Based in Yokohama, JP· patent location history
2011–2013Based in Kanagawa, JP· patent location history
2012–2013Patents assigned to MORIKADO MUTSUO (9)· patent assignee history
2012Patents assigned to ARAI FUMITAKA (1)· patent assignee history
2012Patents assigned to MARUYAMA TOHRU (1)· patent assignee history
2012–2013Based in Yokkaichi, JP· patent location history
2013Based in Mie, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TOSHIBA KK | 19 | 1999–2013 |
| MORIKADO MUTSUOself | 9 | 2012–2013 |
| IBM | 2 | 1995–2002 |
| ARAI FUMITAKA | 1 | 2012 |
| MARUYAMA TOHRU | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Yokohama, JP | 12 | 2002–2013 |
| Yokkaichi, JP | 3 | 2012–2013 |
| Kanagawa, JP | 2 | 2011–2013 |
| Mie, JP | 1 | 2013 |
| Poughkeepsie, New York, US | 1 | 1999 |