Inventor
Mammen Thomas
Inventor
San Jose, CA, US
Overview
Patents· 54 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices23%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1019%
H04LTransmission of digital information, e.g. telegraphic communication13%
G11CStatic stores10%
G06FElectric digital data processing9%
H10BElectronic memory devices9%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%
A61BDiagnosis1%
PatentTitleYear
10,841,227Network congestion and packet reordering202010,110,498Networking using PCI express20189,749,246'Network congestion avoidance'20179,554,772'Non-invasive imager for medical applications'20179,519,608'PCI express to PCI express based low latency interconnect scheme for clustering systems'20169,479,442'Method for congestion avoidance'20168,811,400'Method for identifying next hop'20148,189,603'PCI express to PCI express based low latency interconnect scheme for clustering systems'20128,139,574'Creation and transmission of part of protocol information corresponding to network packets or datalink frames separately'20127,606,248'Method and apparatus for using multiple network processors to achieve higher performance networking applications'20097,583,530'Multi-bit memory technology (MMT) and cells'20097,376,014'Highly reliable NAND flash memory using five side enclosed floating gate storage elements'20087,339,943'Apparatus and method for queuing flow management between input, intermediate and output queues'20087,336,669'Mechanism for distributing statistics across multiple elements'20087,277,437'Packet classification method'20077,227,786'Location-specific NAND (LS NAND) memory technology and cells'20077,224,620'CAcT-Tg (CATT) low voltage NVM cells'20077,206,857'Method and apparatus for a network processor having an architecture that supports burst writes and/or reads'20077,193,900'CACT-TG (CATT) low voltage NVM cells'20077,149,125'Location-specific NAND (LS NAND) memory technology and cells'20066,150,199'Method for fabrication of programmable interconnect structure'20005,989,943'Method for fabrication of programmable interconnect structure'19995,780,919'Electrically programmable interconnect structure having a PECVD amorphous silicon element'19985,717,230'Field programmable gate array having reproducible metal-to-metal amorphous silicon antifuses'19985,691,949'Very high density wafer scale device architecture'19975,675,161'Channel accelerated tunneling electron cell, with a select region incorporated, for high density low power applications'19975,519,653'Channel accelerated carrier tunneling-(CACT) method for programming memories'19965,514,884'Very high density wafer scale device architecture'19965,506,431'Double poly trenched channel accelerated tunneling electron (DPT-CATE) cell, for memory applications'19965,502,315'Electrically programmable interconnect structure having a PECVD amorphous silicon element'19965,315,130'Very high density wafer scale device architecture'19945,252,507'Very high density wafer scale device architecture'19935,223,741'Package for an integrated circuit structure'19935,182,632'High density multichip package with interconnect structure and heatsink'19934,929,992'MOS transistor construction with self aligned silicided contacts to gate, source, and drain regions'19904,922,318'Bipolar and MOS devices fabricated on same integrated circuit substrate'19904,808,548'Method of making bipolar and MOS devices on same integrated circuit substrate'19894,800,171'Method for making bipolar and CMOS integrated circuit structures'19894,789,760'Via in a planarized dielectric and process for producing same'19884,707,456'Method of making a planar structure containing MOS and bipolar transistors'19874,696,095'Process for isolation using self-aligned diffusion process'19874,688,314'Method of making a planar MOS device in polysilicon'19874,686,763'Method of making a planar polysilicon bipolar device'19874,682,409'Fast bipolar transistor for integrated circuit structure and method for forming same'19874,672,420'Integrated circuit structure having conductive, protective layer for multilayer metallization to permit reworking'19874,669,179'Integrated circuit fabrication process for forming a bipolar transistor having extrinsic base regions'19874,669,180'Method of forming emitter coupled logic bipolar memory cell using polysilicon Schottky diodes for coupling'19874,654,824'Emitter coupled logic bipolar memory cell'19874,639,288'Process for formation of trench in integrated circuit structure using isotropic and anisotropic etching'19874,635,230'Emitter coupled logic bipolar memory cell'19874,616,404'Method of making improved lateral polysilicon diode by treating plasma etched sidewalls to remove defects'19864,481,070'Double planarization process for multilayer metallization of integrated circuit structures'19844,468,285'Plasma etch process for single-crystal silicon with improved selectivity to silicon dioxide'19844,456,501'Process for dislocation-free slot isolations in device fabrication'1984Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1984–1990Patents assigned to ADVANCED MICRO DEVICES INC (20)· patent assignee history
1984–2012Based in San Jose, CA, US· patent location history
1993–1997Patents assigned to TACTICAL FABS INC (6)· patent assignee history
2006–2020Patents assigned to THOMAS MAMMEN (15)· patent assignee history
2007–2009Patents assigned to ALTERA CORP (5)· patent assignee history
2007–2020Based in Hercules, CA, US· patent location history
2012–2020Patents assigned to GEORGE SUSAN (6)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 20 | 1984–1990 |
| THOMAS MAMMENself | 15 | 2006–2020 |
| GEORGE SUSAN | 6 | 2012–2020 |
| TACTICAL FABS INC | 6 | 1993–1997 |
| ALTERA CORP | 5 | 2007–2009 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 43 | 1984–2012 |
| Hercules, California, US | 11 | 2007–2020 |