Inventor
Leonard GULER
Inventor
US
Overview
Patents· 16 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices33%
H01LSemiconductor devices24%
B82YSpecific uses or applications of nanostructures18%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
H10BElectronic memory devices2%
PatentTitleYear
12,484,207SRAM with channel count contrast for greater read stability202512,426,316Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material202512,405,526Extreme ultraviolet lithography patterning with assist features202512,369,393Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach202512,349,394Dielectric isolation layer between a nanowire transistor and a substrate202512,328,905Cavity spacer for nanowire transistors202512,131,991Self aligned gratings for tight pitch interconnects and methods of fabrication202412,002,810Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach202411,929,396Cavity spacer for nanowire transistors202411,901,458Dielectric isolation layer between a nanowire transistor and a substrate202411,569,231Non-planar transistors with channel regions having varying widths202311,538,937Fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material202211,404,578Dielectric isolation layer between a nanowire transistor and a substrate202211,342,411Cavity spacer for nanowire transistors202211,251,117Self aligned gratings for tight pitch interconnects and methods of fabrication202211,189,614Process etch with reduced loading effect2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2025Patents assigned to INTEL CORP (16)· patent assignee history
2021–2025Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 16 | 2021–2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 16 | 2021–2025 |