Inventor
Li-Te Lin
Inventor
Hsinchu, TW
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1035%
H10DInorganic electric semiconductor devices22%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%
H01LSemiconductor devices17%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
H01JElectric discharge tubes or discharge lamps2%
H10BElectronic memory devices2%
G06FElectric digital data processing1%
H04WWireless communication networks1%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use1%
PatentTitleYear
10,861,953Air spacers in transistors and methods forming same202010,861,745Semiconductor device and method of manufacture202010,861,706Etch selectivity improved by laser beam202010,861,698Pattern fidelity enhancement202010,847,633Method for forming semiconductor device202010,790,195Elongated pattern and formation thereof202010,777,455Multi-etching process for forming via opening in semiconductor device structure202010,755,943Method for manufacturing semiconductor device202010,755,968Method of forming semiconductor structure having layer with re-entrant profile202010,741,671Method for manufacturing semiconductor device202010,707,081Fine line patterning methods202010,680,109CMOS semiconductor device having fins and method of fabricating the same202010,645,650Computer power saving method and computer waking method202010,535,520Fin patterning methods for increased process margins202010,164,067Method of fabricating a semiconductor device201810,157,773Semiconductor structure having layer with re-entrant profile and method of forming the same201810,157,751Method for manufacturing semiconductor device201810,032,887Method of forming a contact20189,627,258'Method of forming a contact'20179,196,491'End-cut first approach for critical dimension control'20158,563,410'End-cut first approach for critical dimension control'20138,404,546'Source/drain carbon implant and RTA anneal, pre-SiGe deposition'20138,212,253'Shallow junction formation and high dopant activation rate of MOS devices'20128,039,375'Shallow junction formation and high dopant activation rate of MOS devices'20117,838,887'Source/drain carbon implant and RTA anneal, pre-SiGe deposition'20107,816,217'Multi-step epitaxial process for depositing Si/SiGe'20107,612,389'Embedded SiGe stressor with tensile strain for NMOS current enhancement'20097,494,884'SiGe selective growth without a hard mask'20097,446,050'Etching and plasma treatment process to improve a gate profile'20087,390,753'In-situ plasma treatment of advanced resists in fine pattern definition'20087,307,009'Phosphoric acid free process for polysilicon gate definition'20077,253,112'Dual damascene process'20077,179,715'Method for controlling spacer oxide loss'20077,109,085'Etching process to avoid polysilicon notching'20066,864,174'Iteratively selective gas flow control and dynamic database to achieve CD uniformity'20056,849,531'Phosphoric acid free process for polysilicon gate definition'20056,835,578'Test structure for differentiating the line and via contribution in stress migration'20046,797,627'Dry-wet-dry solvent-free process after stop layer etch in dual damascene process'20046,797,630'Partial via hard mask open on low-k dual damascene etch with dual hard mask (DHM) approach'20046,794,302'Dynamic feed forward temperature control to achieve CD etching uniformity'20046,743,732'Organic low K dielectric etch with NH3 chemistry'20046,720,256'Method of dual damascene patterning'20046,551,938'N2/H2 chemistry for dry development in top surface imaging technology'20036,495,469'High selectivity, low etch depth micro-loading process for non stop layer damascene etch'20026,407,002'Partial resist free approach in contact etch to improve W-filling'20026,376,366'Partial hard mask open process for hard mask dual damascene etch'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2015Patents assigned to TAIWAN SEMICONDUCTOR MFG (26)· patent assignee history
2002–2020Based in Hsinchu, TW· patent location history
2005–2013Based in Hsinchu County, TW· patent location history
2012–2013Patents assigned to LIN LI-TE S (3)· patent assignee history
2012–2013Patents assigned to NIEH CHUN-FENG (2)· patent assignee history
2013Patents assigned to CHANG HSUN (1)· patent assignee history
2017–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (18)· patent assignee history
2020Based in New Taipei, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 26 | 2002–2015 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 18 | 2017–2020 |
| LIN LI-TE Sself | 3 | 2012–2013 |
| NIEH CHUN-FENG | 2 | 2012–2013 |
| CHANG HSUN | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 41 | 2002–2020 |
| Hsinchu County, TW | 4 | 2005–2013 |
| New Taipei, TW | 1 | 2020 |