Inventor
Wu-Shiung Feng
Inventor
Taoyuan, TW
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing65%
A61BDiagnosis5%
C07CAcyclic or carbocyclic compounds5%
G01RMeasuring electric variables5%
H03FAmplifiers5%
H03HImpedance networks, e.g. resonant circuits5%
H04WWireless communication networks5%
Y02PClimate change mitigation technologies in the production or processing of goods5%
PatentTitleYear
11,129,072Systems, methods, and apparatuses for managing multiple anchors for multi-homing20219,181,167'Chemically-modified graphene and method for producing the same'20157,797,140'Generalizations of adjoint networks techniques for RLC interconnects model-order reductions'20107,738,947'Biomedical signal instrumentation amplifier'20107,600,206'Method of estimating the signal delay in a VLSI circuit'20097,562,324'Method of designing a synchronous circuit of VLSI for clock skew scheduling and optimization'20097,512,525'Multi-point model reductions of VLSI interconnects using the rational Arnoldi method with adaptive orders'20097,509,243'Method of determining high-speed VLSI reduced-order interconnect by non-symmetric lanczos algorithm'20097,437,689'Interconnect model-order reduction method'20087,398,499'Method of searching paths suffering from the electrostatic discharge in the process of an integrated circuit design'20087,373,367'Efficient digital filter design tool for approximating an FIR filter with a low-order linear-phase IIR filter'20087,254,790'Method of moment computations in R(L)C interconnects of high speed VLSI with resistor loops'20077,216,322'Clock tree synthesis for low power consumption and low clock skew'20077,216,309'Method and apparatus for model-order reduction and sensitivity analysis'20077,191,418'Method and apparatus for rapidly selecting types of buffers which are inserted into the clock tree for high-speed very-large-scale-integration'20077,181,664'Method on scan chain reordering for lowering VLSI power consumption'20077,124,381'Method of estimating crosstalk noise in lumped RLC coupled interconnects'20067,017,130'Method of verification of estimating crosstalk noise in coupled RLC interconnects with distributed line in nanometer integrated circuits'2006D0361159'Lipstick case'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995Patents assigned to FENG WU S (1)· patent assignee history
1995–2015Based in Taipei, TW· patent location history
2006–2015Patents assigned to UNIV CHANG GUNG (17)· patent assignee history
2006–2010Based in Taoyuan, TW· patent location history
2008Based in Kuei Shan Hsiang, TW· patent location history
2015Patents assigned to CHEN HSIAO-CHIEN (1)· patent assignee history
2015Patents assigned to CHEN SHI-LIANG (1)· patent assignee history
2021Patents assigned to APPLE INC (1)· patent assignee history
2021Based in Tigard, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| UNIV CHANG GUNG | 17 | 2006–2015 |
| APPLE INC | 1 | 2021 |
| CHEN HSIAO-CHIEN | 1 | 2015 |
| CHEN SHI-LIANG | 1 | 2015 |
| FENG WU Sself | 1 | 1995 |
Locations
| Location | Patents | Span |
|---|---|---|
| Taoyuan, TW | 15 | 2006–2010 |
| Taipei, TW | 2 | 1995–2015 |
| Tigard, OR, US | 1 | 2021 |
| Kuei Shan Hsiang, TW | 1 | 2008 |