Inventor

Mark T. Ramsbey

Inventor

Sunnyvale, CA, US

Overview

1997–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 156 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary

H10BElectronic memory devices35%

H10DInorganic electric semiconductor devices25%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests10%

H01LSemiconductor devices5%

G11CStatic stores2%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%

B82YSpecific uses or applications of nanostructures0%

H10NElectric solid-state devices not otherwise provided for0%

PatentTitleYear

11,056,646Memory device having programmable impedance elements with a common conductor formed below bit lines2021 10,984,861Reference circuits and methods for resistive memories2021 10,923,601Charge trapping split gate device and method of fabricating same2021 10,818,761Memory first process flow and device2020 10,777,568Split gate charge trapping memory cells having different select gate and memory gate heights2020 10,403,731Memory first process flow and device2019 10,141,393Three dimensional capacitor2018 10,014,380Memory first process flow and device2018 9,966,477Charge trapping split gate device and method of fabricating same2018 9,922,833'Charge trapping split gate embedded flash memory and associated methods'2018 9,917,166'Memory first process flow and device'2018 9,590,079'Use disposable gate cap to form transistors, and split gate charge trapping memory cells'2017 9,368,606'Memory first process flow and device'2016 9,368,644'Gate formation memory by planarization'2016 9,209,197'Memory gate landing pad made from dummy features'2015 8,957,472'Memory device having trapezoidal bitlines and method of fabricating same'2015 8,816,438'Process charging protection for split gate charge trapping flash'2014 8,691,647'Memory devices containing a high-K dielectric layer'2014 8,673,716'Memory manufacturing process with bitline isolation'2014 8,368,219'Buried silicide local interconnect with sidewall spacers and method for making the same'2013 8,125,018'Memory device having trapezoidal bitlines and method of fabricating same'2012 8,049,334'Buried silicide local interconnect with sidewall spacers and method for making the same'2011 7,972,948'Method for forming bit lines for semiconductor devices'2011 7,964,905'Anti-reflective interpoly dielectric'2011 7,811,915'Method for forming bit lines for semiconductor devices'2010 7,786,003'Buried silicide local interconnect with sidewall spacers and method for making the same'2010 7,670,936'Nitridation of gate oxide by laser processing'2010 7,507,661'Method of forming narrowly spaced flash memory contact openings and lithography masks'2009 7,432,178'Bit line implant'2008 7,414,277'Memory cell having combination raised source and drain and method of fabricating same'2008 7,394,125'Recessed channel with separated ONO memory device'2008 7,256,141'Interface layer between dual polycrystalline silicon layers'2007 7,176,113'LDC implant for mirrorbit to improve Vt roll-off and form sharper junction'2007 7,163,860'Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device'2007 7,157,335'Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi bit memory devices'2007 7,115,469'Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process'2006 7,067,377'Recessed channel with separated ONO memory device'2006 7,060,554'PECVD silicon-rich oxide layer for reduced UV charging'2006 7,053,446'Memory wordline spacer'2006 7,033,957'ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices'2006 7,018,896'UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing'2006 7,018,868'Disposable hard mask for memory bitline scaling'2006 7,012,008'Dual spacer process for non-volatile memory devices'2006 7,001,807'Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same'2006 7,001,814'Laser thermal annealing methods for flash memory devices'2006 6,992,370'Memory cell structure having nitride layer with reduced charge loss and method for fabricating same'2006 6,989,320'Bitline implant utilizing dual poly'2006 6,989,319'Methods for forming nitrogen-rich regions in non-volatile semiconductor memory devices'2006 6,987,048'Memory device having silicided bitlines and method of forming the same'2006 6,969,654'Flash NVROM devices with UV charge immunity'2005 6,962,849'Hard mask spacer for sublithographic bitline'2005 6,958,272'Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell'2005 6,958,511'Flash memory device and method of fabrication thereof including a bottom oxide layer with two regions with different concentrations of nitrogen'2005 6,927,145'Bitline hard mask spacer flow for memory cell scaling'2005 6,912,163'Memory device having high work function gate and method of erasing same'2005 6,900,085'ESD implant following spacer deposition'2005 6,884,681'Method of manufacturing a semiconductor memory with deuterated materials'2005 6,872,643'Implant damage removal by laser thermal annealing'2005 6,867,097'Method of making a memory cell with polished insulator layer'2005 6,861,307'Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same'2005 6,855,608'Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance'2005 6,828,199'Monos device having buried metal silicide bit line'2004 6,808,996'Method for protecting gate edges from charge gain/loss in semiconductor device'2004 6,803,272'Use of high-K dielectric material in modified ONO structure for semiconductor devices'2004 6,798,002'Dual-purpose anti-reflective coating and spacer for flash memory and other dual gate technologies and method of forming'2004 6,794,764'Charge-trapping memory arrays resistant to damage from contact hole information'2004 6,787,840'Nitridated tunnel oxide barriers for flash memory technology circuitry'2004 6,783,591'Laser thermal annealing method for high dielectric constant gate oxide films'2004 6,774,432'UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL'2004 6,773,988'Memory wordline spacer'2004 6,770,938'Diode fabrication for ESD/EOS protection'2004 6,753,570'Memory device and method of making'2004 6,735,123'High density dual bit flash memory cell with non planar structure'2004 6,730,564'Salicided gate for virtual ground arrays'2004 6,727,143'Method and system for reducing charge gain and charge loss when using an ARC layer in interlayer dielectric formation'2004 6,720,133'Memory manufacturing process using disposable ARC for wordline formation'2004 6,707,078'Dummy wordline for erase and bitline leakage'2004 6,706,595'Hard mask process for memory device without bitline shorts'2004 6,680,509'Nitride barrier layer for protection of ONO structure from top oxide loss in fabrication of SONOS flash memory'2004 6,674,138'Use of high-k dielectric materials in modified ONO structure for semiconductor devices'2004 6,670,241'Semiconductor memory with deuterated materials'2003 6,667,243'Etch damage repair with thermal annealing'2003 6,653,191'Memory manufacturing process using bitline rapid thermal anneal'2003 6,653,190'Flash memory with controlled wordline width'2003 6,645,801'Salicided gate for virtual ground arrays'2003 6,642,573'Use of high-K dielectric material in modified ONO structure for semiconductor devices'2003 6,639,271'Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same'2003 6,635,943'Method and system for reducing charge gain and charge loss in interlayer dielectric formation'2003 6,630,384'Method of fabricating double densed core gates in sonos flash memory'2003 6,630,383'Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer'2003 6,627,945'Memory device and method of making'2003 6,620,717'Memory with disposable ARC for wordline formation'2003 6,617,215'Memory wordline hard mask'2003 6,605,511'Method of forming nitridated tunnel oxide barriers for flash memory technology circuitry and STI and LOCOS isolation'2003 6,589,841'Charge gain/charge loss junction leakage prevention for flash technology by using double isolation/capping layer between lightly doped drain and gate'2003 6,579,778'Source bus formation for a flash memory using silicide'2003 6,573,151'Method of forming zero marks'2003 6,566,194'Salicided gate for virtual ground arrays'2003 6,555,436'Simultaneous formation of charge storage and bitline to wordline isolation'2003 6,548,855'Non-volatile memory dielectric as charge pump dielectric'2003 6,548,334'Capping layer'2003 6,541,816'Planar structure for non-volatile memory devices'2003 6,509,604'Nitridation barriers for nitridated tunnel oxide for circuitry for flash technology and for LOCOS/STI isolation'2003 6,500,713'Method for repairing damage to charge trapping dielectric layer from bit line implantation'2002 6,486,029'Integration of an ion implant hard mask structure into a process for fabricating high density memory cells'2002 6,479,348'Method of making memory wordline hard mask extension'2002 6,475,847'Method for forming a semiconductor device with self-aligned contacts using a liner oxide layer'2002 6,468,865'Method of simultaneous formation of bitline isolation and periphery oxide'2002 6,465,306'Simultaneous formation of charge storage and bitline to wordline isolation'2002 6,465,835'Charge gain/charge loss junction leakage prevention for flash technology by using double isolation/capping layer between lightly doped drain and gate'2002 6,465,303'Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory'2002 6,455,373'Semiconductor device having gate edges protected from charge gain/loss'2002 6,448,608'Capping layer'2002 6,444,530'Process for fabricating an integrated circuit with a self-aligned contact'2002 6,440,797'Nitride barrier layer for protection of ONO structure from top oxide loss in a fabrication of SONOS flash memory'2002 6,436,768'Source drain implant during ONO formation for improved isolation of SONOS devices'2002 6,436,766'Process for fabricating high density memory cells using a polysilicon hard mask'2002 6,433,383'Methods and arrangements for forming a single interpoly dielectric layer in a semiconductor device'2002 6,420,752'Semiconductor device with self-aligned contacts using a liner oxide layer'2002 6,410,443'Method for removing semiconductor ARC using ARC CMP buffing'2002 6,403,420'Nitrogen implant after bit-line formation for ONO flash memory devices'2002 6,399,446'Process for fabricating high density memory cells using a metallic hard mask'2002 6,399,984'Species implantation for minimizing interface defect density in flash memory devices'2002 6,369,416'Semiconductor device with contacts having a sloped profile'2002 6,342,415'Method and system for providing reduced-sized contacts in a semiconductor device'2002 6,337,246'Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing'2002 6,291,296'Method for removing anti-reflective coating layer using plasma etch process before contact CMP'2001 6,284,600'Species implantation for minimizing interface defect density in flash memory devices'2001 6,274,433'Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices'2001 6,268,624'Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing'2001 6,252,276'Non-volatile semiconductor memory device including assymetrically nitrogen doped gate oxide'2001 6,251,717'Viable memory cell formed using rapid thermal annealing'2001 6,248,627'Method for protecting gate edges from charge gain/loss in semiconductor device'2001 6,235,584'Method and system for reducing short channel effects in a memory device'2001 6,235,587'Method of manufacturing a semiconductor device with reduced arc loss in peripheral circuitry region'2001 6,232,630'Light floating gate doping to improve tunnel oxide reliability'2001 6,211,020'Process for fabricating a common source region in memory devices'2001 6,200,857'Method of manufacturing a semiconductor device without arc loss in peripheral circuit region'2001 6,197,635'Method of manufacturing a semiconductor device with reduced masking and without ARC loss in peripheral circuitry region'2001 6,160,317'Method of spacer formation and source protection after self-aligned source formed and a device provided by such a method'2000 6,136,510'Doubled-sided wafer scrubbing for improved photolithography'2000 6,136,649'Method for removing anti-reflective coating layer using plasma etch process after contact CMP'2000 6,133,619'Reduction of silicon oxynitride film delamination in integrated circuit inter-level dielectrics'2000 6,034,394'Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices'2000 6,030,868'Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation'2000 6,001,713'Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device'1999 5,981,364'Method of forming a silicon gate to produce silicon devices with improved performance'1999 5,972,751'Methods and arrangements for introducing nitrogen into a tunnel oxide in a non-volatile semiconductor memory device'1999 5,966,618'Method of forming dual field isolation structures'1999 5,933,730'Method of spacer formation and source protection after self-aligned source is formed and a device provided by such a method'1999 5,907,781'Process for fabricating an integrated circuit with a self-aligned contact'1999 5,899,726'Method of forming oxide isolation in a semiconductor device'1999 5,869,385'Selectively oxidized field oxide region'1999 5,780,204'Backside wafer polishing for improved photolithography'1998 5,747,882'Device including means for preventing tungsten silicide lifting, and method of fabrication thereof'1998 5,624,859'Method for providing device isolation and off-state leakage current for a semiconductor device'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2013Patents assigned to ADVANCED MICRO DEVICES INC (117)· patent assignee history

1997–2021Based in Sunnyvale, CA, US· patent location history

1999–2004Patents assigned to FUJITSU LTD (15)· patent assignee history

2004–2008Patents assigned to FASL LLC (8)· patent assignee history

2006–2016Patents assigned to SPANSION LLC (20)· patent assignee history

2015–2021Patents assigned to CYPRESS SEMICONDUCTOR CORP (13)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ADVANCED MICRO DEVICES INC	117	1997–2013
SPANSION LLC	20	2006–2016
FUJITSU LTD	15	1999–2004
CYPRESS SEMICONDUCTOR CORP	13	2015–2021
FASL LLC	8	2004–2008

Locations

Location	Patents	Span
Sunnyvale, California, US	156	1997–2021