LexDanaLexDanabeta
Inventor

Lacky V. Shah

Inventor
Los Altos Hills, CA, US

Overview

61→
Patents
1998–2021
Patent span
Physics
Primary field (CPC G)

Patents· 61 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing74%
G06TImage data processing or generation, in general11%
H04LTransmission of digital information, e.g. telegraphic communication11%
A61BDiagnosis1%
G01RMeasuring electric variables1%
G16HHealthcare informatics, i.e. information and communication technology [ict] specially adapted for the handling or processing of medical or healthcare data1%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
PatentTitleYear
10,959,642Methods and systems of evaluating axonal loss and demyelination202110,795,722Compute task state encapsulation202010,552,201Software-assisted instruction level execution preemption202010,552,202Software-assisted instruction level execution preemption202010,430,915Multi-GPU frame rendering201910,402,323Organizing memory to optimize memory accesses of compressed data201910,402,937Multi-GPU frame rendering201910,289,418Cooperative thread array granularity context switch during trap handling201910,235,208Technique for saving and restoring thread group operating state201910,217,183System, method, and computer program product for simultaneous execution of compute and graphics workloads201910,095,542Cooperative thread array granularity context switch during trap handling20189,934,145Organizing memory to optimize memory accesses of compressed data20189,921,873'Controlling work distribution for processing tasks'20189,804,885'Cooperative thread array granularity context switch during trap handling'20179,720,858'Technique for performing memory access operations via texture hardware'20179,715,413'Execution state analysis for assigning tasks to streaming multiprocessors'20179,710,874'Mid-primitive graphics execution preemption'20179,697,006'Technique for performing memory access operations via texture hardware'20179,678,897'Approach for context switching of lock-bit protected memory'20179,652,282'Software-assisted instruction level execution preemption'20179,654,548'Intelligent network streaming and execution system for conventionally coded applications'20179,513,975'Technique for computational nested parallelism'20169,507,638'Compute work distribution reference counters'20169,448,837'Cooperative thread array granularity context switch during trap handling'20169,442,759'Concurrent execution of independent streams in multi-channel time slice groups'20169,348,762'Technique for accessing content-addressable memory'20169,147,224'Method for handling state transitions in a network of virtual processing nodes'20159,130,953'Intelligent network streaming and execution system for conventionally coded applications'20159,069,609'Scheduling and execution of compute tasks'20158,984,183'Signaling, ordering, and execution of dynamically generated tasks in a processing system'20158,976,185'Method for handling state transitions in a network of virtual processing nodes'20158,948,167'System and method for using domains to identify dependent and independent operations'20158,893,249'Intelligent network streaming and execution system for conventionally coded applications'20148,831,995'Optimized server for streamed applications'20148,438,298'Intelligent network streaming and execution system for conventionally coded applications'20138,095,782'Multiple simultaneous context architecture for rebalancing contexts on multithreaded processing cores upon a context change'20127,873,793'Supporting speculative modification in a data cache'20117,725,885'Method and apparatus for trace based adaptive run time compiler'20107,606,979'Method and system for conservatively managing store capacity available to a processor issuing stores'20097,386,861'System and method for efficiently blocking event signals associated with an operating system'20087,225,299'Supporting speculative modification in a data cache'20077,149,851'Method and system for conservatively managing store capacity available to a processor issuing stores'20067,062,567'Intelligent network streaming and execution system for conventionally coded applications'20067,043,524'Network caching system for streamed applications'20066,959,320'Client-side performance optimization system for streamed applications'20056,658,486'System and method for efficiently blocking event signals associated with an operating system'20036,622,300'Dynamic optimization of computer programs using code-rewriting kernal module'20036,327,704'System, method, and product for multi-branch backpatching in a dynamic translator'20016,295,644'Method and apparatus for patching program text to improve performance of applications'20016,223,339'System, method, and product for memory management in a dynamic translator'20016,205,545'Method and apparatus for using static branch predictions hints with dynamically translated code traces to improve performance'20016,189,141'Control path evaluating trace designator with dynamically adjustable thresholds for activation of tracing for high (hot) activity and low (cold) activity of flow control'20016,164,841'Method, apparatus, and product for dynamic software code translation system'20006,148,437'System and method for jump-evaluated trace designation'20006,115,809'Compiling strong and weak branching behavior instruction blocks to separate caches for dynamic and static prediction'20006,112,280'Method and apparatus for distinct instruction pointer storage in a partitioned cache memory'20006,052,530'Dynamic translation system and method for optimally translating computer code'20005,933,622'Method for efficient handling of asynchronous events in a dynamic translation system'19995,911,073'Method and apparatus for dynamic process monitoring through an ancillary control code system'19995,797,013'Intelligent loop unrolling'19985,721,893'Exploiting untagged branch prediction cache by relocating branches'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2001Patents assigned to HEWLETT PACKARD CO (14)· patent assignee history
1998–2014Based in Fremont, CA, US· patent location history
1999–2010Based in Sunnyvale, CA, US· patent location history
2012–2020Patents assigned to NVIDIA CORP (30)· patent assignee history
2012–2020Patents assigned to SHAH LACKY V (13)· patent assignee history
2012–2020Based in Los Altos Hills, CA, US· patent location history
2013–2014Based in San Jose, CA, US· patent location history
2015–2020Patents assigned to DULUK JR JEROME F (7)· patent assignee history
2015–2020Patents assigned to TREICHLER SEAN J (7)· patent assignee history
2018–2019Based in Los Altos, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
NVIDIA CORP302012–2020
HEWLETT PACKARD CO141998–2001
SHAH LACKY Vself132012–2020
DULUK JR JEROME F72015–2020
TREICHLER SEAN J72015–2020
Locations
LocationPatentsSpan
Los Altos Hills, California, US302012–2020
Sunnyvale, California, US141999–2010
Fremont, California, US121998–2014
Los Altos, California, US22018–2019
San Jose, California, US22013–2014