Inventor
Shigetoshi Wakayama
Inventor
Kawasaki, JP
Overview
Patents· 17 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores20%
H04LTransmission of digital information, e.g. telegraphic communication20%
H03KPulse technique17%
G06FElectric digital data processing14%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use9%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
G01RMeasuring electric variables3%
H03FAmplifiers3%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses3%
H10BElectronic memory devices3%
PatentTitleYear
8,468,481'Support program, design support system, and design support method'20138,065,553'Phase interpolator for a timing signal generating circuit'20117,642,624'Semiconductor device having a guard ring'20107,496,781'Timing signal generating circuit with a master circuit and slave circuits'20097,342,434'Semiconductor device including capacitor having decoupling capacity'20087,256,474'Semiconductor device having a guard ring'20077,106,108'Semiconductor integrated circuit and evaluation method of wiring in the same'20067,096,375'Data transfer circuit between different clock regions'20066,493,394'SIGNAL TRANSMISSION SYSTEM FOR TRANSMITTING SIGNALS BETWEEN LSI CHIPS, RECEIVER CIRCUIT FOR USE IN THE SIGNAL TRANSMISSION SYSTEM, AND SEMICONDUCTOR MEMORY DEVICE APPLYING THE SIGNAL TRANSMISSION SYSTEM'20026,484,268'Signal transmission system having a timing adjustment circuit'20026,377,638'SIGNAL TRANSMISSION SYSTEM FOR TRANSMITTING SIGNALS BETWEEN LSI CHIPS, RECEIVER CIRCUIT FOR USE IN THE SIGNAL TRANSMISSION SYSTEM, AND SEMICONDUCTOR MEMORY DEVICE APPLYING THE SIGNAL TRANSMISSION SYSTEM'20026,333,883'Destructive read type memory circuit, restoring circuit for the same and sense amplifier'20016,247,138'Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system'20016,218,713'Logical circuit, flip-flop circuit and storage circuit with multivalued logic'20016,205,076'Destructive read type memory circuit, restoring circuit for the same and sense amplifier'20016,157,688'Signal transmission system for transmitting signals between LSI chips, receiver circuit for use in the signal transmission system, and semiconductor memory device applying the signal transmission system'20006,064,244'Phase-locked loop circuit permitting reduction of circuit size'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2011Patents assigned to FUJITSU LTD (15)· patent assignee history
2000–2011Based in Kawasaki, JP· patent location history
2010Patents assigned to FUJITSU MICROELECTRONICS LTD (1)· patent assignee history
2011–2013Patents assigned to WAKAYAMA SHIGETOSHI (2)· patent assignee history
2011Patents assigned to GOTOH KOHTAROH (1)· patent assignee history
2013Patents assigned to FUJITSU SEMICONDUCTOR LTD (1)· patent assignee history
2013Based in Yokohama, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| FUJITSU LTD | 15 | 2000–2011 |
| WAKAYAMA SHIGETOSHIself | 2 | 2011–2013 |
| FUJITSU MICROELECTRONICS LTD | 1 | 2010 |
| FUJITSU SEMICONDUCTOR LTD | 1 | 2013 |
| GOTOH KOHTAROH | 1 | 2011 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kawasaki, JP | 16 | 2000–2011 |
| Yokohama, JP | 1 | 2013 |