Inventor
Matthew Berzins
Inventor
Cedar Park, TX, US
Overview
Patents· 33 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique41%
G06FElectric digital data processing11%
G11CStatic stores8%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use8%
G01RMeasuring electric variables6%
H10DInorganic electric semiconductor devices6%
H01LSemiconductor devices5%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
G01SRadio direction-finding2%
H03CModulation2%
PatentTitleYear
11,092,649Method for reducing power consumption in scannable flip-flops without additional circuitry202110,819,342Low-power low-setup integrated clock gating cell with complex enable selection202010,784,864Low power integrated clock gating system and method202010,784,198Power rail for standard cell block202010,748,889Power grid and standard cell co-design structure and methods thereof202010,720,204System and method for improving scan hold-time violation and low voltage operation in sequential circuit202010,607,982Layout connection isolation technique for improving immunity to jitter and voltage drop in a standard cell202010,581,410High speed domino-based flip flop202010,382,017Dynamic flip flop having data independent P-stack feedback201910,353,000Multi-bit flip-flops201910,298,235Low power integrated clock gating cell using controlled inverted clock201910,262,723System and method for improving scan hold-time violation and low voltage operation in sequential circuit20199,904,758'Using deep sub-micron stress effects and proximity effects to create a high performance standard cell'20189,899,990'Semiconductor circuit including flip-flop'20189,891,283'Multi-bit flip-flops and scan chain circuits'20189,793,881'Flip-flop with zero-delay bypass mux'20179,779,201'Low power minimal disruptive method to implement large quantity push and pull useful-skew schedules with enabling circuits in a clock-mesh based design'20179,768,756'Low power integrated clock gating cell with internal control signal'20179,564,897'Apparatus for low power high speed integrated clock gating cell'20179,473,117'Multi-bit flip-flops and scan chain circuits'20169,450,578'Integrated clock gater (ICG) using clock cascode complimentary switch logic'20169,419,590'Low power toggle latch-based flip-flop including integrated clock gating logic'20169,203,382'Integrated clock gater (ICG) using clock cascode complimentary switch logic'20158,975,949'Integrated clock gater (ICG) using clock cascode complimentary switch logic'20158,289,060'Pulsed state retention power gating flip-flop'20127,826,581'Linearized digital phase-locked loop method for maintaining end of packet time linearity'20107,683,697'Circuitry and method for buffering a power mode control signal'20107,583,121'Flip-flop having logic state retention during a power down mode and method therefor'20097,394,293'Circuit and method for rapid power up of a differential output driver'20087,239,178'Circuit and method for CMOS voltage level translation'20077,176,720'Low duty cycle distortion differential to CMOS translator'20077,173,453'Method and circuit for translating a differential signal to complementary CMOS levels'20076,781,465'Method and apparatus for differential signal detection'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2010Patents assigned to CYPRESS SEMICONDUCTOR CORP (6)· patent assignee history
2004–2019Based in Austin, TX, US· patent location history
2007–2021Based in Cedar Park, TX, US· patent location history
2009–2012Patents assigned to FREESCALE SEMICONDUCTOR INC (3)· patent assignee history
2012–2015Patents assigned to BERZINS MATTHEW S (3)· patent assignee history
2015–2021Patents assigned to SAMSUNG ELECTRONICS CO LTD (24)· patent assignee history
2016–2020Patents assigned to BERZINS MATTHEW (7)· patent assignee history
2016Based in Hwasung, KR· patent location history
2018Based in Hwaswung, KR· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SAMSUNG ELECTRONICS CO LTD | 24 | 2015–2021 |
| BERZINS MATTHEWself | 7 | 2016–2020 |
| CYPRESS SEMICONDUCTOR CORP | 6 | 2004–2010 |
| BERZINS MATTHEW Sself | 3 | 2012–2015 |
| FREESCALE SEMICONDUCTOR INC | 3 | 2009–2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cedar Park, Texas, US | 25 | 2007–2021 |
| Austin, Texas, US | 6 | 2004–2019 |
| Hwaswung, KR | 1 | 2018 |
| Hwasung, KR | 1 | 2016 |