Inventor
Paul Leventis
Inventor
Toronto, CA
Overview
Patents· 41 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique60%
G06FElectric digital data processing25%
A63FCard, board, or roulette games4%
G11CStatic stores4%
G06TImage data processing or generation, in general2%
H03MCoding2%
H04LTransmission of digital information, e.g. telegraphic communication2%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
PatentTitleYear
11,110,348Memory management in gaming rendering202111,077,364Resolution-based scaling of real-time interactive graphics20219,576,095'Partial reconfiguration compatibility detection in an integrated circuit device'20179,489,480'Techniques for compiling and generating a performance analysis for an integrated circuit design'20169,094,014'PLD architecture for flexible placement of IP function blocks'20158,732,646'PLD architecture for flexible placement of IP function blocks'20148,694,946'Simultaneous switching noise optimization'20148,443,321'Pessimism removal in the modeling of simultaneous switching noise'20138,407,649'PLD architecture for flexible placement of IP function blocks'20138,201,129'PLD architecture for flexible placement of IP function blocks'20128,191,025'Redundancy structures and methods in a programmable logic device'20128,103,975'Apparatus and methods for optimizing the performance of programmable logic devices using multiple supply voltage'20128,099,692'Power-driven timing analysis and placement for programmable logic'20127,983,880'Simultaneous switching noise analysis using superposition techniques'20117,861,190'Power-driven timing analysis and placement for programmable logic'20107,671,626'Versatile logic element and logic array block'20107,656,191'Distributed memory in field-programmable gate array integrated circuit devices'20107,644,386'Redundancy structures and methods in a programmable logic device'20107,584,447'PLD architecture for flexible placement of IP function blocks'20097,432,734'Versatile logic element and logic array block'20087,400,167'Apparatus and methods for optimizing the performance of programmable logic devices'20087,391,236'Distributed memory in field-programmable gate array integrated circuit devices'20087,304,499'Distributed random access memory in a programmable logic device'20077,253,660'Multiplexing device including a hardwired multiplexer in a programmable logic device'20077,236,633'Data compression and decompression techniques for programmable circuits'20077,218,133'Versatile logic element and logic array block'20077,185,306'Method and apparatus for enhancing signal routability'20077,180,324'Redundancy structures and methods in a programmable logic device'20077,132,852'Routing architecture with high speed I/O bypass path'20067,098,687'Flexible routing resources in a programmable logic device'20067,084,665'Distributed random access memory in a programmable logic device'20067,058,920'Methods for designing PLD architectures for flexible placement of IP function blocks'20066,970,014'Routing architecture for a programmable logic device'20056,965,249'Programmable logic device with redundant circuitry'20056,937,064'Versatile logic element and logic array block'20056,895,570'System and method for optimizing routing lines in a programmable logic device'20056,859,065'Use of dangling partial lines for interfacing in a PLD'20056,826,741'Flexible I/O routing resources'20046,653,862'Use of dangling partial lines for interfacing in a PLD'20036,630,842'Routing architecture for a programmable logic device'20036,605,962'PLD architecture for flexible placement of IP function blocks'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2017Patents assigned to ALTERA CORP (39)· patent assignee history
2003–2021Based in Toronto, CA· patent location history
2005–2010Based in Ontario, CA· patent location history
2012–2014Patents assigned to LEVENTIS PAUL (7)· patent assignee history
2012–2013Patents assigned to LEWIS DAVID (4)· patent assignee history
2012Patents assigned to BETZ VAUGHN (2)· patent assignee history
2013–2014Patents assigned to AZIZI NAVID (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ALTERA CORP | 39 | 2003–2017 |
| LEVENTIS PAULself | 7 | 2012–2014 |
| LEWIS DAVID | 4 | 2012–2013 |
| AZIZI NAVID | 2 | 2013–2014 |
| BETZ VAUGHN | 2 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Toronto, CA | 39 | 2003–2021 |
| Ontario, CA | 2 | 2005–2010 |