Inventor
Robert S. Horton
Inventor
Colchester, VT, US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing58%
G06TImage data processing or generation, in general17%
G09GArrangements or circuits for control of indicating devices using static means to present variable information8%
H03KPulse technique8%
H04LTransmission of digital information, e.g. telegraphic communication4%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation4%
PatentTitleYear
9,317,434'Managing out-of-order memory command execution from multiple queues while maintaining data coherency'20169,319,040'Distributing multiplexing logic to remove multiplexor latency on the output path for variable clock cycle, delayed signals'20169,164,908'Managing out-of-order memory command execution from multiple queues while maintaining data coherency'20159,026,763'Managing out-of-order memory command execution from multiple queues while maintaining data coherency'20159,021,228'Managing out-of-order memory command execution from multiple queues while maintaining data coherency'20158,994,424'Distributing multiplexing logic to remove multiplexor latency on the output path for variable clock cycle, delayed signals'20158,341,588'Semiconductor layer forming method and structure'20128,181,148'Method for identifying and implementing flexible logic block logic for easy engineering changes'20128,141,028'Structure for identifying and implementing flexible logic block logic for easy engineering changes'20128,060,845'Minimizing impact of design changes for integrated circuit designs'20117,757,032'Computer system bus bridge'20107,480,888'Design structure for facilitating engineering changes in integrated circuits'20097,469,312'Computer system bus bridge'20087,206,886'Data ordering translation between linear and interleaved domains at a bus interface'20077,065,602'Circuit and method for pipelined insertion'20066,525,738'Display list processor for decoupling graphics subsystem operations from a host processor'20036,177,944'Two phase rendering for computer graphics'20016,052,129'Method and apparatus for deferred clipping of polygons'20005,659,671'Method and apparatus for shading graphical images in a data processing system'19975,434,967'Decision variable hardware logic and processing methods for graphics display system'19955,309,552'Programmable multi-format display controller'19945,303,340'Concave polygon drawing method and processor for a computer graphics display system'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–2016Patents assigned to IBM (22)· patent assignee history
1994–1997Based in Hurley, NY, US· patent location history
2000–2016Based in Colchester, VT, US· patent location history
2011–2012Patents assigned to HERZL ROBERT D (4)· patent assignee history
2011–2012Patents assigned to HORTON ROBERT S (4)· patent assignee history
2011–2012Patents assigned to LAURICELLA KENNETH A (4)· patent assignee history
2011–2012Patents assigned to MILTON DAVID W (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 22 | 1994–2016 |
| HERZL ROBERT D | 4 | 2011–2012 |
| HORTON ROBERT Sself | 4 | 2011–2012 |
| LAURICELLA KENNETH A | 4 | 2011–2012 |
| MILTON DAVID W | 4 | 2011–2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Colchester, VT, US | 18 | 2000–2016 |
| Hurley, New York, US | 4 | 1994–1997 |