Inventor
Thomas A. Piazza
Inventor
Granite Bay, CA, US
Overview
Patents· 67 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Tprimary
G06TImage data processing or generation, in general39%
G06FElectric digital data processing34%
G09GArrangements or circuits for control of indicating devices using static means to present variable information11%
G11CStatic stores10%
H04NPictorial communication, e.g. television4%
G06KGraphical data reading1%
PatentTitleYear
10,410,081Method and apparatus for a high throughput rasterizer201910,297,001Reduced power implementation of computer instructions201910,269,154Rasterization based on partial spans201910,204,051Technique to share information among different cache coherency domains201910,152,764Hardware based free lists for multi-rate shader201810,078,590Technique to share information among different cache coherency domains201810,037,621Hierarchical quadrant based coverage testing for rasterization20189,984,430Ordering threads as groups in a multi-threaded, multi-core graphics compute system20189,983,884Method and apparatus for SIMD structured branching20189,946,650Technique to share information among different cache coherency domains20189,928,170'Scatter/gather capable system coherent cache'20189,824,412'Position-only shading pipeline'20179,741,154'Recording the results of visibility tests at the input geometry object granularity'20179,665,488'Technique to share information among different cache coherency domains'20179,619,859'Techniques for efficient GPU triangle list adjacency detection and handling'20179,601,092'Dynamically managing memory footprint for tile based rendering'20179,471,492'Scatter/gather capable system coherent cache'20169,245,324'Lossy color merge for multi-sampling anti-aliasing compression'20169,235,926'Techniques for improving MSAA rendering efficiency'20169,087,392'Techniques for efficient GPU triangle list adjacency detection and handling'20159,035,962'Technique to share information among different cache coherency domains'20159,035,960'Technique to share information among different cache coherency domains'20159,035,959'Technique to share information among different cache coherency domains'20158,914,800'Behavioral model based multi-threaded architecture'20148,902,915'Dataport and methods thereof'20148,643,660'Technique to share information among different cache coherency domains'20148,601,177'Dynamic allocation of a buffer across multiple clients in a threaded processor'20138,544,019'Thread queueing method and apparatus'20138,448,179'Processing architecture having passive threads and active semaphores'20138,279,886'Dataport and methods thereof'20128,271,986'Visual and graphical data processing using a multi-threaded architecture'20128,225,012'Dynamic allocation of a buffer across multiple clients in a threaded processor'20128,171,225'Cache for a multi thread and multi core system and methods thereof'20128,072,451'Efficient Z testing'20117,975,272'Thread queuing method and apparatus'20117,904,907'Processing architecture having passive threads and active semaphores'20117,719,540'Render-cache controller for multithreading, multi-core graphics processor'20107,614,054'Behavioral model based multi-threaded architecture'20097,603,544'Dynamic allocation of a buffer across multiple clients in multi-threaded processor without performing a complete flush of data associated with allocation'20097,532,765'Run length encoded digital image'20097,526,124'Match MSB digital image compression'20097,439,986'Pixel filtering using shared filter resource between overlay and texture mapping engines'20087,434,028'Hardware stack having entries with a data portion and associated counter'20087,414,632'Multi-pass 4:2:0 subpicture blending'20087,268,779'Z-buffering techniques for graphics rendering'20077,212,676'Match MSB digital image compression'20077,158,147'Method and apparatus for pixel filtering using shared filter resource between overlay and texture mapping engines'20077,139,890'Methods and arrangements to interface memory'20067,051,172'Memory arbiter with intelligent page gathering logic'20067,050,063'3-D rendering texture caching scheme'20067,035,984'Memory arbiter with grace and ceiling periods and intelligent page gathering logic'20066,950,108'Bandwidth reduction for rendering using vertex data'20056,792,516'Memory arbiter with intelligent page gathering logic'20046,762,765'Bandwidth reduction for zone rendering via split vertex buffers'20046,760,031'Upgrading an integrated graphics subsystem'20046,710,784'Method and apparatus for performing a vertical scale filter function in a graphics device using a single line buffer'20046,639,598'Method and apparatus for effective level of detail selection'20036,466,226'Method and apparatus for pixel filtering using shared filter resource between overlay and texture mapping engines'20026,433,790'Methods and systems for rendering line and point features for display'20026,393,579'Method and apparatus for saving power and improving performance in a collapsable pipeline using gated clocks'20026,330,646'Arbitration mechanism for a computer system having a unified memory architecture'20016,204,857'Method and apparatus for effective level of detail selection'20016,191,793'Method and apparatus for texture level of detail dithering'20016,091,428'Frame buffer memory system for reducing page misses when rendering with color and Z buffers'20006,072,505'Method and apparatus to efficiently interpolate polygon attributes in two dimensions at a prescribed clock rate'20005,367,615'Spatial augmentation of vertices and continuous level of detail transition for smoothly varying terrain polygon density'19944,958,305'Polygon edge clipping'1990Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1990Based in Orange County, FL, US· patent location history
1994Based in Port Orange, FL, US· patent location history
2000–2019Based in Granite Bay, CA, US· patent location history
2001–2019Patents assigned to INTEL CORP (61)· patent assignee history
2012–2019Patents assigned to PIAZZA THOMAS A (13)· patent assignee history
2012–2014Patents assigned to JIANG HONG (5)· patent assignee history
2012–2019Patents assigned to DWYER MICHAEL K (3)· patent assignee history
2014–2015Patents assigned to BERKOVITS ARIEL (3)· patent assignee history
2018–2019Based in Setauket, NY, US· patent location history
2019Based in New York, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 61 | 2001–2019 |
| PIAZZA THOMAS Aself | 13 | 2012–2019 |
| JIANG HONG | 5 | 2012–2014 |
| BERKOVITS ARIEL | 3 | 2014–2015 |
| DWYER MICHAEL K | 3 | 2012–2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Granite Bay, California, US | 61 | 2000–2019 |
| Setauket, New York, US | 3 | 2018–2019 |
| New York, New York, US | 1 | 2019 |
| Port Orange, Florida, US | 1 | 1994 |
| Orange County, Florida, US | 1 | 1990 |