Inventor
Rohit A. Vidwans
Inventor
Beaverton, OR, US
Overview
Patents· 11 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing85%
G11CStatic stores15%
PatentTitleYear
7,159,154'Technique for synchronizing faults in a processor having a replay system'20076,643,742'Method and system for efficient cache memory updating with a least recently used (LRU) protocol'20036,629,271'Technique for synchronizing faults in a processor having a replay system'20035,889,982'Method and apparatus for generating event handler vectors based on both operating mode and event type'19995,826,069'Having write merge and data override capability for a superscalar processing device'19985,777,928'Multi-port register'19985,778,220'Method and apparatus for disabling interrupts in a highly pipelined processor'19985,740,393'Instruction pointer limits in processor that performs speculative out-of-order instruction execution'19985,708,843'Method and apparatus for handling code segment violations in a computer system'19985,574,935'Superscalar processor with a multi-port reorder buffer'19965,463,745'Methods and apparatus for determining the next instruction pointer in an out-of-order execution computer system'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2007Patents assigned to INTEL CORP (11)· patent assignee history
1995–1999Based in Beaverton, OR, US· patent location history
1998–2007Based in Portland, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 11 | 1995–2007 |
Locations
| Location | Patents | Span |
|---|---|---|
| Beaverton, OR, US | 7 | 1995–1999 |
| Portland, OR, US | 4 | 1998–2007 |