Inventor
Arjun Kar-Roy
Inventor
Irvine, CA, US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1040%
H10DInorganic electric semiconductor devices23%
H01LSemiconductor devices15%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
B81BMicrostructural devices or systems, e.g. micromechanical devices4%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems4%
G01JMeasurement of intensity, velocity, spectral content, polarisation, phase or pulse characteristics of infrared, visible or ultraviolet light4%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein2%
PatentTitleYear
10,615,071Structure having isolated deep substrate vias with decreased pitch and increased aspect ratio and related method202010,615,072Structure having isolated deep substrate vias with decreased pitch and increased aspect ratio and related method20209,887,123'Structure having isolated deep substrate vias with decreased pitch and increased aspect ratio and related method'20189,458,011'Scalable self-supported MEMS structure and related method'20169,377,350'Light sensor with chemically resistant and robust reflector stack'20169,346,669'Robust MEMS structure with via cap and related method'20169,136,157'Deep N wells in triple well structures'20159,105,681'Method for forming deep silicon via for grounding of circuits and devices, emitter ballasting and isolation'20158,598,713'Deep silicon via for grounding of circuits and devices, emitter ballasting and isolation'20138,212,331'Method for fabricating a backside through-wafer via in a processed wafer and related structure'20128,098,351'Self-planarized passivation dielectric for liquid crystal on silicon structure and related method'20127,897,484'Fabricating a top conductive layer in a semiconductor die'20117,772,673'Deep trench isolation and method for forming same'20107,704,874'Method for fabricating a frontside through-wafer via in a processed wafer and related structure'20107,589,009'Method for fabricating a top conductive layer in a semiconductor die and related structure'20097,078,310'Method for fabricating a high density composite MIM capacitor with flexible routing in semiconductor dies'20067,052,966'Deep N wells in triple well structures and method for fabricating same'20067,041,569'Method for fabricating a high density composite MIM capacitor with reduced voltage dependence in semiconductor dies'20066,777,777'High density composite MIM capacitor with flexible routing in semiconductor dies'20046,680,521'High density composite MIM capacitor with reduced voltage dependence in semiconductor dies'20046,430,028'Method for fabrication of an MIM capacitor and related structure'20026,411,492'Structure and method for fabrication of an improved capacitor'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2020Patents assigned to NEWPORT FAB LLC (21)· patent assignee history
2002Patents assigned to CONEXANT SYSTEMS INC (1)· patent assignee history
2002–2020Based in Irvine, CA, US· patent location history
2012–2015Patents assigned to KAR-ROY ARJUN (4)· patent assignee history
2012–2015Patents assigned to RACANELLI MARCO (3)· patent assignee history
2013Patents assigned to BLASCHKE VOLKER (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NEWPORT FAB LLC | 21 | 2002–2020 |
| KAR-ROY ARJUNself | 4 | 2012–2015 |
| RACANELLI MARCO | 3 | 2012–2015 |
| BLASCHKE VOLKER | 1 | 2013 |
| CONEXANT SYSTEMS INC | 1 | 2002 |
Locations
| Location | Patents | Span |
|---|---|---|
| Irvine, California, US | 22 | 2002–2020 |