Inventor
Sameer Pradhan
Inventor
Portland, OR, US
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices28%
H01LSemiconductor devices27%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1019%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
C22CAlloys4%
C23CCoating metallic material4%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein1%
PatentTitleYear
10,770,591Source/drain contacts for non-planar transistors202010,693,006Interlayer dielectric for non-planar transistors202010,283,640Source/drain contacts for non-planar transistors201910,056,488Interlayer dielectric for non-planar transistors201810,020,375Tungsten gates for non-planar transistors20189,893,148'Method for fabricating a transistor device with a tuned dopant profile'20189,853,156Source/drain contacts for non-planar transistors20179,812,546'Tungsten gates for non-planar transistors'20179,637,810'Tungsten gates for non-planar transistors'20179,634,124'Interlayer dielectric for non-planar transistors'20179,580,776'Tungsten gates for non-planar transistors'20179,577,041'Method for fabricating a transistor device with a tuned dopant profile'20179,490,347'Capping dielectric structures for transistor gates'20169,425,316'Source/drain contacts for non-planar transistors'20169,368,624'Method for fabricating a transistor with reduced junction leakage current'20169,299,801'Method for fabricating a transistor device with a tuned dopant profile'20169,202,699'Capping dielectric structure for transistor gates'20159,196,727'High uniformity screen and epitaxial layers for CMOS devices'20159,177,867'Tungsten gates for non-planar transistors'20159,112,057'Semiconductor devices with dopant migration suppression and method of fabrication thereof'20159,105,711'Semiconductor structure with reduced junction leakage and method of fabrication thereof'20159,087,915'Interlayer dielectric for non-planar transistors'20159,041,126'Deeply depleted MOS transistors having a screening layer and methods thereof'20158,981,435'Source/drain contacts for non-planar transistors'20158,883,600'Transistor having reduced junction leakage and methods of forming thereof'20148,877,619'Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom'20148,637,955'Semiconductor structure with reduced junction leakage and method of fabrication thereof'20147,751,654'Electro-optic modulation'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2020Based in Portland, OR, US· patent location history
2014–2015Patents assigned to SUVOLTA INC (4)· patent assignee history
2014–2015Patents assigned to PRADHAN SAMEER (3)· patent assignee history
2014–2018Based in San Jose, CA, US· patent location history
2015–2020Patents assigned to INTEL CORP (16)· patent assignee history
2015–2018Patents assigned to MIE FUJITSU SEMICONDUCTOR LTD (8)· patent assignee history
2015Patents assigned to PRADHAN SAMEER S (3)· patent assignee history
2015–2016Based in Campbell, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 16 | 2015–2020 |
| MIE FUJITSU SEMICONDUCTOR LTD | 8 | 2015–2018 |
| SUVOLTA INC | 4 | 2014–2015 |
| PRADHAN SAMEERself | 3 | 2014–2015 |
| PRADHAN SAMEER Sself | 3 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 16 | 2010–2020 |
| San Jose, California, US | 9 | 2014–2018 |
| Campbell, California, US | 3 | 2015–2016 |