Inventor
Kevin J. Lee
Inventor
Beaverton, OR, US
Overview
Patents· 64 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
H01LSemiconductor devices14%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
A61KPreparations for medical, dental or toiletry purposes4%
H10BElectronic memory devices4%
H10NElectric solid-state devices not otherwise provided for4%
A61PSpecific therapeutic activity of chemical compounds or medicinal preparations3%
C07KPeptides3%
C12NMicroorganisms or enzymes3%
G06FElectric digital data processing3%
PatentTitleYear
10,811,595Techniques for forming logic including integrated spin-transfer torque magnetoresistive random-access memory202010,790,263Integrated circuit die having backside passive components and methods associated therewith202010,644,064Logic chip including embedded magnetic tunnel junctions202010,455,308Die with integrated microphone device using through-silicon vias (TSVs)201910,290,598Method and apparatus for forming backside die planar devices and saw filter201910,224,309Integrated circuit die having backside passive components and methods associated therewith20199,997,563Logic chip including embedded magnetic tunnel junctions20189,911,689'Through-body-via isolated coaxial capacitor and techniques for forming same'20189,852,964Through-body via formation techniques20179,721,886'Preservation of fine pitch redistribution lines'20179,716,066'Interconnect structure comprising fine pitch backside metal redistribution lines combined with vias'20179,660,181'Logic chip including embedded magnetic tunnel junctions'20179,530,740'3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach'20169,489,354'Masking content while preserving layout of a webpage'20169,449,913'3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias'20169,252,111'Method for handling very thin device wafers'20169,142,510'3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach'20159,041,146'Logic chip including embedded magnetic tunnel junctions'20159,018,184'Inhibitors of SP140 and their use in therapy'20158,994,174'Structure having a planar bonding surface'20158,935,620'Dynamic content management'20158,933,564'Landing structure for through-silicon via'20158,910,927'Work holding device for an archery bow'20148,887,085'Dynamic content navigation'20148,853,757'Forming thick metal interconnect structures for integrated circuits'20148,704,336'Selective removal of on-die redistribution interconnects from scribe-lines'20148,691,747'Method of treatment based on ATAD2 inhibitors'20148,349,845'Thiazolopyrimidines for use in therapy'20138,297,605'Multipurpose ball joint assembly and work holding devices'20128,104,172'Method buffer coating having a physical mixture of high toughness polymer and a low shrinkage polymer'20128,017,398'Method for assaying protein-protein interaction'20117,982,311'Solder limiting layer for integrated circuit die copper bumps'20117,964,965'Forming thick metal interconnect structures for integrated circuits'20117,833,899'Multi-layer thick metallization structure for a microelectronic device, intergrated circuit containing same, and method of manufacturing an integrated circuit containing same'20107,785,809'Nucleic acids and proteins of insect Or83b odorant receptor genes and uses thereof'20107,759,321'Compounds for the treatment of pain'20107,732,936'Buffer coating having a physical mixture of high toughness polymer and a low shrinkage polymer'20107,601,829'Nucleic acids and proteins of insect Or83b odorant receptor genes and uses thereof'20097,585,615'Composite photoresist for modifying die-side bumps'20097,550,574'Nucleic acids and proteins of insect Or83b odorant receptor genes and uses thereof'20097,498,252'Dual layer dielectric stack for microelectronics having thick metal lines'20097,442,634'Method for constructing contact formations'20087,391,112'Capping copper bumps'20087,238,798'Nucleic acids and proteins of insect Or83b odorant receptor genes and uses thereof'20077,088,005'Wafer stacking with anisotropic conductive adhesive'20067,064,446'Under bump metallization layer to enable use of high tin content solder bumps'20067,049,076'Method for assaying protein—protein interaction'20067,030,119'Method for treating chronic pain using MEK inhibitors'20066,984,302'Electroplating cell based upon rotational plating solution flow'20066,943,440'Methods of processing thick ILD layers using spray coating or lamination for C4 wafer level thick metal integrated flow'2005D0494976'Panel of a computer'20046,737,360'Controlled potential anodic etching process for the selective removal of conductive thin films'2004D0477315'Casing for computer mainframe'20036,539,953'Method and apparatus for cleaning a heater bellow in a chemical vapor deposition chamber'20036,384,481'Single step electroplating process for interconnect via fill and metal line patterning'20026,346,144'Chemical-mechanical polishing slurry'20026,304,830'Automatic keyboard testing apparatus'20016,214,098'Chemical-mechanical polishing slurry'20016,077,337'Chemical-mechanical polishing slurry'20006,051,098'Keyboard etching apparatus'2000D0422992'Front panel of a computer'20006,020,266'Single step electroplating process for interconnect via fill and metal line patterning'20005,267,620'Drilling latch apparatus'19934,685,656'Motor racing track fence'1987Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2020Patents assigned to INTEL CORP (40)· patent assignee history
2000–2015Patents assigned to LEE KEVIN (5)· patent assignee history
2000–2020Based in Beaverton, OR, US· patent location history
2000–2004Based in Aloha, OR, US· patent location history
2006–2011Based in New York, NY, US· patent location history
2007–2010Patents assigned to SENTISEARCH INC (4)· patent assignee history
2012–2016Patents assigned to LEE KEVIN J (9)· patent assignee history
2014–2016Patents assigned to AMAZON TECH INC (3)· patent assignee history
2014–2015Based in Stevenage, GB· patent location history
2014–2015Based in Seattle, WA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 40 | 2000–2020 |
| LEE KEVIN Jself | 9 | 2012–2016 |
| LEE KEVINself | 5 | 2000–2015 |
| SENTISEARCH INC | 4 | 2007–2010 |
| AMAZON TECH INC | 3 | 2014–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Beaverton, OR, US | 36 | 2000–2020 |
| New York, New York, US | 6 | 2006–2011 |
| Aloha, OR, US | 4 | 2000–2004 |
| Stevenage, GB | 2 | 2014–2015 |
| Seattle, Washington, US | 2 | 2014–2015 |