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Inventor

Max F. Hineman

Inventor
Boise, ID, US

Overview

46→
Patents
1997–2017
Patent span
Electricity
Primary field (CPC H)

Patents· 46 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%
C11DDetergent compositions9%
H10BElectronic memory devices8%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%
H10DInorganic electric semiconductor devices7%
H10NElectric solid-state devices not otherwise provided for7%
B82YSpecific uses or applications of nanostructures5%
H01LSemiconductor devices5%
H01JElectric discharge tubes or discharge lamps4%
PatentTitleYear
9,837,604Phase-change memory cell implant for dummy array leakage reduction20179,608,042'Electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques'20179,559,146'Phase-change memory cell implant for dummy array leakage reduction'20179,299,747'Electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques'20169,231,202'Thermal-disturb mitigation in dual-deck cross-point memories'20169,082,714'Use of etch process post wordline definition to improve data retention in a flash memory device'20158,809,198'Nano-crystal etch process'20148,673,787'Method to reduce charge buildup during high aspect ratio contact etch'20148,568,900'Methods for forming an enriched metal oxide surface'20137,985,692'Method to reduce charge buildup during high aspect ratio contact etch'20117,659,210'Nano-crystal etch process'20107,615,164'Plasma etching methods and contact opening forming methods'20097,396,774'Methods for forming an enriched metal oxide surface'20087,344,975'Method to reduce charge buildup during high aspect ratio contact etch'20087,319,071'Methods for forming a metallic damascene structure'20087,293,526'Plasma reaction chamber liner consisting essentially of osmium'20077,255,803'Method of forming contact openings'20077,211,849'Protective layers for MRAM devices'20077,166,543'Methods for forming an enriched metal oxide surface for use in a semiconductor device'20077,135,444'Cleaning composition useful in semiconductor integrated circuit fabrication'20067,131,391'Plasma reaction chamber liner comprising ruthenium'20067,118,683'Methods of etching silicon-oxide-containing compositions'20067,087,561'Cleaning composition useful in semiconductor integrated circuit fabrication'20067,067,429'Processing method of forming MRAM circuitry'20067,067,466'Cleaning composition useful in semiconductor integrated circuit fabrication'20067,067,465'Cleaning composition useful in semiconductor integrated circuit fabricating'20066,953,531'Methods of etching silicon-oxide-containing materials'20056,844,255'Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry'20056,841,525'Dilute cleaning composition and method for using same'20056,831,047'Cleaning composition useful in semiconductor integrated circuit fabrication'20046,797,628'Methods of forming integrated circuitry, semiconductor processing methods, and processing method of forming MRAM circuitry'20046,783,995'Protective layers for MRAM devices'20046,638,843'Method for forming a silicide gate stack for use in a self-aligned contact etch'20036,596,647'Dilute cleaning composition and method for using the same'20036,547,979'Methods of enhancing selectivity of etching silicon dioxide relative to one or more organic substances; and plasma reaction chambers'20036,521,931'Self-aligned, magnetoresitive random-access memory (MRAM) structure utilizing a spacer containment scheme'20036,486,108'Cleaning composition useful in semiconductor integrated circuit fabrication'20026,384,001'Dilute cleaning composition'20026,379,872'Etching of anti-reflective coatings'20026,372,657'Method for selective etching of oxides'20026,358,756'Self-aligned, magnetoresistive random-access memory (MRAM) structure utilizing a spacer containment scheme'20026,350,679'Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry'20026,313,048'Dilute cleaning composition and method for using same'20016,136,767'Dilute composition cleaning method'20006,136,670'Semiconductor processing methods of forming contacts between electrically conductive materials'20005,689,334'Intracavity laser spectroscope for high sensitivity detection of contaminants'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2017Based in Boise, ID, US· patent location history
2000–2014Patents assigned to MICRON TECHNOLOGY INC (39)· patent assignee history
2008–2011Based in Sunnyvale, CA, US· patent location history
2013–2014Patents assigned to HINEMAN MAX (2)· patent assignee history
2014–2015Patents assigned to HINEMAN MAX F (2)· patent assignee history
2014Patents assigned to ALAPATI RAMAKANTH (1)· patent assignee history
2015–2017Patents assigned to INTEL CORP (6)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MICRON TECHNOLOGY INC392000–2014
INTEL CORP62015–2017
HINEMAN MAXself22013–2014
HINEMAN MAX Fself22014–2015
ALAPATI RAMAKANTH12014
Locations
LocationPatentsSpan
Boise, ID, US441997–2017
Sunnyvale, California, US22008–2011