Inventor
Kyung Suk Oh
Inventor
Cupertino, CA, US
Overview
Patents· 76 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores26%
H03KPulse technique19%
G06FElectric digital data processing18%
H01LSemiconductor devices11%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
H04LTransmission of digital information, e.g. telegraphic communication6%
H05KPrinted circuits2%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
G01RMeasuring electric variables1%
H01BCables1%
PatentTitleYear
10,879,225Semiconductor package and method of manufacturing semiconductor package202010,861,826Substrate assembly semiconductor package including the same and method of manufacturing the semiconductor package202010,854,551Semiconductor package and method of fabricating the same202010,797,021Semiconductor packages having improved thermal discharge and electromagnetic shielding characteristics202010,770,124Memory device comprising programmable command-and-address and/or data interfaces202010,756,015Semiconductor package, package-on-package device, and method of fabricating the same202010,748,871Semiconductor chip and semiconductor package including the same202010,727,199Electronic device including semiconductor device package202010,720,196On-die termination of address and command signals202010,699,983Semiconductor package202010,674,597Structure for delivering power202010,651,849Transaction-based on-die termination202010,541,201Semiconductor package, package-on-package device, and method of fabricating the same202010,536,304Receiver with clock recovery circuit and adaptive sample and equalizer timing202010,510,388On-die termination of address and command signals201910,270,442Memory component with on-die termination201910,268,252Changing settings for a transient period associated with a deterministic event201910,192,598Memory device comprising programmable command-and-address and/or data interfaces201910,115,439On-die termination of address and command signals201810,056,902On-die termination control20189,941,201Magnetically decoupled inductor structures20189,935,052Power line layout in integrated circuits20189,913,363'Structure for delivering power'20189,870,040'Changing settings for a transient period associated with a deterministic event'20189,859,358'On-die capacitor (ODC) structure'20189,842,181'Method to optimize general-purpose input/output interface pad assignments for integrated circuit'20179,836,428Reducing unwanted reflections in source-terminated channels20179,818,471'Circuitry and methods for measuring and correcting duty-cycle distortion'20179,748,934'Systems and methods for reducing power supply noise or jitter'20179,734,879'Memory device comprising programmable command-and-address and/or data interfaces'20179,721,629'On-die termination of address and command signals'20179,660,648'On-die termination control'20179,570,129'On-die termination of address and command signals'20179,461,631'Circuitry and methods for measuring and correcting duty-cycle distortion'20169,455,825'Receiver with clock recovery circuit and adaptive sample and equalizer timing'20169,342,095'Timing calibration for multimode I/O systems'20169,337,835'Controlling a flash device having time-multiplexed, on-die-terminated signaling interface'20169,306,566'Nonvolatile memory with command-driven on-die termination'20169,306,568'Controlling on-die termination in a nonvolatile memory'20169,306,567'Memory device with programmed device address and on-die-termination'20169,304,568'Changing settings for a transient period associated with a deterministic event'20169,306,564'Nonvolatile memory device with on-die control and data signal termination'20169,306,565'Nonvolatile memory with chip-select/device-address triggered on-die termination'20169,299,407'On-die termination of address and command signals'20169,231,601'Techniques relating to phase-locked loop circuits'20169,225,328'Nonvolatile memory device with time-multiplexed, on-die-terminated signaling interface'20159,178,688'Receiver with clock recovery circuit and adaptive sample and equalizer timing'20159,166,583'Buffered memory module having multi-valued on-die termination'20159,153,572'Integrated circuit system with dynamic decoupling and method of manufacture thereof'20159,135,206'Command-triggered on-die termination'20159,117,496'Memory device comprising programmable command-and-address and/or data interfaces'20159,059,695'Methods and systems for reducing supply and termination noise'20158,981,811'Multi-valued on-die termination'20158,947,962'On-die termination of address and command signals'20158,922,245'Power saving driver design'20148,878,592'Simultaneous switching noise cancellation by adjusting reference voltage and sampling clock phase'20148,836,384'Systems and methods for reducing power supply noise or jitter'20148,692,574'Methods and systems for reducing supply and termination noise'20148,692,573'Signal lines with internal and external termination'20148,610,459'Controlling on-die termination in a dynamic random access memory device'20138,610,455'Dynamic on-die termination selection'20138,599,631'On-die termination of address and command signals'20138,588,012'Balanced on-die termination'20138,588,280'Asymmetric communication on shared links'20138,548,110'Receiver with clock recovery circuit and adaptive sample and equalizer timing'20138,451,913'Frequency responsive bus coding'20138,188,762'Controlling dynamic selection of on-die termination'20128,130,010'Signal lines with internal and external termination'20128,089,298'Integrated circuit device with dynamically selected on-die termination'20127,924,048'Memory controller that controls termination in a memory device'20117,915,912'Signal lines with internal and external termination'20117,782,082'Memory-module buffer with on-die termination'20107,602,209'Controlling memory devices that have on-die termination'20097,486,104'Integrated circuit with graduated on-die termination'20097,236,894'Circuits, systems and methods for dynamic reference voltage calibration'20077,162,376'Circuits, systems and methods for dynamic reference voltage calibration'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2020Patents assigned to RAMBUS INC (57)· patent assignee history
2007–2013Based in Campbell, CA, US· patent location history
2011–2020Based in Cupertino, CA, US· patent location history
2012–2018Patents assigned to OH KYUNG SUK (13)· patent assignee history
2012–2013Patents assigned to SHAEFFER IAN P (5)· patent assignee history
2014–2018Patents assigned to ALTERA CORP (10)· patent assignee history
2020Patents assigned to SAMSUNG ELECTRONICS CO LTD (9)· patent assignee history
2020Based in Seongnam-si, KR· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| RAMBUS INC | 57 | 2007–2020 |
| OH KYUNG SUKself | 13 | 2012–2018 |
| ALTERA CORP | 10 | 2014–2018 |
| SAMSUNG ELECTRONICS CO LTD | 9 | 2020 |
| SHAEFFER IAN P | 5 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cupertino, California, US | 55 | 2011–2020 |
| Campbell, California, US | 12 | 2007–2013 |
| Seongnam-si, KR | 9 | 2020 |