Inventor
Kok Heng Choe
Inventor
Penang, MY
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores34%
H03KPulse technique34%
G06FElectric digital data processing21%
H04BTransmission3%
H04LTransmission of digital information, e.g. telegraphic communication3%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
PatentTitleYear
10,536,174Interface for efficient usage of communication circuitry20209,912,337'Systems and methods for configuring an SOPC without a need to use an external memory'20189,543,956'Systems and methods for configuring an SOPC without a need to use an external memory'20179,275,694'FPGA equivalent input and output grid muxing on structural ASIC memory'20169,130,561'Configuring a programmable logic device using a configuration bit stream without phantom bits'20158,910,102'Configuring a programmable logic device using a configuration bit stream without phantom bits'20148,885,392'RAM/ROM memory circuit'20148,645,450'Multiplier-accumulator circuitry and methods'20148,261,141'Real time feedback compensation of programmable logic memory'20127,901,999'FPGA equivalent input and output grid muxing on structural ASIC memory'20117,882,408'Real time feedback compensation of programmable logic memory'2011RE041325'Dual port random-access-memory circuitry'20107,679,397'Techniques for precision biasing output driver for a calibrated on-chip termination circuit'20107,586,327'Distributed memory circuitry on structured application-specific integrated circuit devices'20097,542,324'FPGA equivalent input and output grid muxing on structural ASIC memory'20097,471,588'Dual port random-access-memory circuitry'20087,319,619'Programmable logic device memory blocks with adjustable timing'20087,164,289'Real time feedback compensation of programmable logic memory'20077,071,731'Programmable Logic with Pipelined Memory Operation'20067,046,566'Voltage-based timing control of memory bit lines'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2018Patents assigned to ALTERA CORP (18)· patent assignee history
2006–2016Based in Penang, MY· patent location history
2012–2017Patents assigned to CHOE KOK HENG (5)· patent assignee history
2012Patents assigned to CHUA KAR KENG (1)· patent assignee history
2015–2018Based in Bayan Lepas, MY· patent location history
2017–2020Patents assigned to INTEL CORP (2)· patent assignee history
2017Patents assigned to HOOI WOI JIE (1)· patent assignee history
2020Based in Sg Ara, MY· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ALTERA CORP | 18 | 2006–2018 |
| CHOE KOK HENGself | 5 | 2012–2017 |
| INTEL CORP | 2 | 2017–2020 |
| CHUA KAR KENG | 1 | 2012 |
| HOOI WOI JIE | 1 | 2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Penang, MY | 16 | 2006–2016 |
| Bayan Lepas, MY | 3 | 2015–2018 |
| Sg Ara, MY | 1 | 2020 |