LexDanaLexDanabeta
Inventor

Weiqi Ding

Inventor
Fremont, CA, US

Overview

77→
Patents
2010–2019
Patent span
Electricity
Primary field (CPC H)

Patents· 77 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H04Lprimary
H04LTransmission of digital information, e.g. telegraphic communication31%
H03KPulse technique17%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses11%
G06FElectric digital data processing7%
G01RMeasuring electric variables5%
H04BTransmission4%
G11CStatic stores3%
H03MCoding3%
H03BGeneration of oscillations, directly or by frequency-changing, by circuits employing active elements which operate in a non-switching manner3%
H01FMagnets2%
PatentTitleYear
10,212,498Integrated circuit device with field programmable optical array20199,979,403Reference clock architecture for integrated circuit device20189,960,937High-speed serial data signal receiver circuitry20189,876,519Methods and apparatus for automated adaptation of transmitter equalizer tap settings20189,680,675'Methods and apparatus for automated adaptation of transmitter equalizer tap settings'20179,660,846'High-speed serial data signal receiver circuitry'20179,654,123'Phase-locked loop architecture and clock distribution system'20179,608,728'Integrated circuit device with field programmable optical array'20179,543,965'Interposer with embedded clock network circuitry'20179,479,181'Reference clock architecture for integrated circuit device'20169,444,656'Flexible receiver architecture'20169,429,625'Analog signal test circuits and methods'20169,401,189'Methods and apparatus for performing runtime data eye monitoring and continuous data strobe calibration'20169,350,530'Phase-locked loop architecture and clock distribution system'20169,222,972'On-die jitter generator'20159,224,685'Shielded metal-oxide-metal (MOM) capacitor structure'20159,203,604'Methods and apparatus for performing bit swapping in clock data recovery circuitry'20159,172,566'Methods and apparatus for multiple-stage CTLE adaptation'20159,166,832'Methods and apparatus for decision feedback equalization adaptation'20159,166,641'Method and apparatus for receiver VGA adaptation'20159,112,655'Clock data recovery circuitry with programmable clock phase selection'20159,106,230'Input-output circuitry for integrated circuits'20159,077,323'Latched comparator circuitry'20159,065,399'Programmable high-speed voltage-mode differential driver'20159,054,721'Systems and methods for digital calibration of successive-approximation-register analog-to-digital converter'20158,989,214'High-speed serial data signal receiver circuitry'20158,958,512'System and method for receiver equalization adaptation'20158,933,751'High resolution capacitor'20158,922,264'Methods and apparatus for clock tree phase alignment'20148,860,469'Apparatus and methods for transmitter output swing calibration'20148,847,626'Circuits and methods for providing clock signals'20148,836,443'Integrated circuits with configurable inductors'20148,837,571'Apparatus and methods for on-die instrumentation'20148,836,384'Systems and methods for reducing power supply noise or jitter'20148,798,127'Apparatus and methods for adaptive receiver delay equalization'20148,754,794'Methods and apparatus for calibrating pipeline analog-to-digital converters'20148,750,406'Multi-level amplitude signaling receiver'20148,744,012'On-chip eye viewer architecture for highspeed transceivers'20148,723,572'Apparatus and methods to correct differential skew and/or duty cycle distortion'20148,705,602'Equalizer circuitry with selectable tap positions and coefficients'20148,692,582'Latched comparator circuitry'20148,674,862'Systems and methods for digital calibration of successive-approximation-register analog-to-digital converter'20148,644,440'Apparatus and methods for detection and correction of transmitter duty cycle distortion'20148,611,403'Apparatus and methods for transceiver power adaptation'20138,610,466'High-speed differential comparator circuitry with accurately adjustable threshold'20138,612,795'Segmented clock network for transceiver array'20138,504,882'Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations'20138,464,088'Multiple channel bonding in a high speed clock network'20138,462,906'Apparatus and methods for detection and correction of transmitter duty cycle distortion'20138,451,883'On-chip full eye viewer architecture'20138,433,958'Bit error rate checker receiving serial data signal from an eye viewer'20138,416,001'Techniques for reducing duty cycle distortion in periodic signals'20138,395,421'Configurable buffer circuits and methods'20138,319,564'Integrated circuits with configurable inductors'20128,290,750'Signal detect for high-speed serial interface'20128,248,107'High-speed differential comparator circuitry with accurately adjustable threshold'20128,228,102'Phase-locked loop architecture and clock distribution system'20128,188,774'Apparatus and methods for activation of an interface on an integrated circuit'20128,184,651'PLD architecture optimized for 10G Ethernet physical layer solution'20128,174,294'Configurable buffer circuits and methods'20128,125,254'Techniques for configuring multi-path feedback loops'20128,126,079'High-speed serial data signal interface circuitry with multi-data-rate switching capability'20128,127,215'Signal loss detector for high-speed serial interface of a programmable logic device'20128,111,784'On-chip data signal eye monitoring circuitry and methods'20128,081,723'Serial data signal eye width estimator methods and apparatus'20118,030,964'Techniques for level shifting signals'20117,999,588'Duty cycle correction circuitry'20117,996,749'Signal loss detector for high-speed serial interface of a programmable logic device'20117,977,984'High-speed charge pump circuits'20117,956,695'High-frequency low-gain ring VCO for clock-data recovery in high-speed serial interface of a programmable logic device'20117,952,423'Process/design methodology to enable high performance logic and analog circuits using a single process'20117,924,046'Configurable emphasis for high-speed transmitter driver circuitry'20117,915,941'Phase interpolator circuits and methods'20117,899,649'Signal detect for high-speed serial interface'20117,821,343'Transmitter with multiple phase locked loops'20107,812,591'High-speed signal detect for serial interface'20107,759,972'Integrated circuit architectures with heterogeneous high-speed serial interface circuitry'2010

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2010–2019Patents assigned to ALTERA CORP (77)· patent assignee history
2010–2019Based in Fremont, CA, US· patent location history
2011–2017Patents assigned to DING WEIQI (38)· patent assignee history
2011–2016Patents assigned to SHUMARAYEV SERGEY (24)· patent assignee history
2011–2015Patents assigned to WONG WILSON (14)· patent assignee history
2012–2015Patents assigned to PAN MINGDE (10)· patent assignee history
2015Based in San Jose, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ALTERA CORP772010–2019
DING WEIQIself382011–2017
SHUMARAYEV SERGEY242011–2016
WONG WILSON142011–2015
PAN MINGDE102012–2015
Locations
LocationPatentsSpan
Fremont, California, US762010–2019
San Jose, California, US12015