Inventor
Kuang Yeu Hsieh
Inventor
Hsinchu, TW
Overview
Patents· 87 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices27%
H10NElectric solid-state devices not otherwise provided for24%
G11CStatic stores22%
H10DInorganic electric semiconductor devices14%
H01LSemiconductor devices4%
B82YSpecific uses or applications of nanostructures3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h101%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h101%
PatentTitleYear
9,240,405'Memory with off-chip controller'20169,076,964'Methods for forming resistance random access memory structure'20159,048,341'Integrated circuit capacitor and method'20159,018,615'Resistor random access memory structure having a defined small area of electrical contact'20158,987,787'Semiconductor structure and method for manufacturing the same'20158,927,956'Resistance type memory device'20158,846,549'Method of forming bottom oxide for nitride flash memory'20148,772,106'Graded metal oxide resistance based semiconductor memory device'20148,722,469'Memory cell and process for manufacturing the same'20148,704,205'Semiconductor structure with improved capacitance of bit line'20148,643,078'Semiconductor structure and manufacturing method of the same'20148,642,398'Resistive random access memory and method for manufacturing the same'20148,604,555'Semiconductor structure and manufacturing method of the same'20138,587,983'Resistance random access memory structure for enhanced retention'20138,488,362'Graded metal oxide resistance based semiconductor memory device'20138,362,615'Memory and manufacturing method thereof'20138,324,681'Stacked non-volatile memory device and methods for fabricating the same'20128,243,494'Self-aligned structure and method for confining a melting point in a resistor random access memory'20128,178,405'Resistor random access memory cell device'20128,158,963'Programmable resistive RAM and manufacturing method'20128,153,485'Method for fabricating memory'20128,139,393'Method and apparatus for non-volatile multi-bit memory'20128,129,706'Structures and methods of a bistable resistive random access memory'20128,114,715'Resistive random access memory and method for manufacturing the same'20128,110,429'Bridge resistance random access memory device and method with a singular contact structure'20128,111,541'Method of a multi-level cell resistance random access memory with metal oxides'20128,106,376'Method for manufacturing a resistor random access memory with a self-aligned air gap insulator'20128,080,440'Resistor random access memory cell with L-shaped electrode'20118,072,810'Program and erase methods with substrate transient hot carrier injections in a non-volatile memory'20118,072,793'High density resistance based semiconductor device'20118,067,762'Resistance random access memory structure for enhanced retention'20118,067,815'Aluminum copper oxide based memory devices and methods for manufacture'20118,039,392'Resistor random access memory cell with reduced active area and reduced contact areas'20118,026,136'Methods of forming low hydrogen concentration charge-trapping layer structures for non-volatile memory'20118,022,489'Air tunnel floating gate memory cell'20118,022,466'Non-volatile memory cells having a polysilicon-containing, multi-layer insulating structure, memory arrays including the same and methods of operating the same'20118,022,465'Low hydrogen concentration charge-trapping layer structures for non-volatile memory'20117,999,295'Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same'20117,989,790'Resistance random access memory'20117,981,742'Semiconductor device, data element thereof and method of fabricating the same'20117,977,227'Method of manufacturing a non-volatile memory device'20117,977,735'Stacked non-volatile memory device and methods for fabricating the same'20117,973,366'Dual-gate, sonos, non-volatile memory cells and arrays thereof'20117,972,893'Memory device manufacturing method'20117,960,224'Operation method for multi-level switching of metal-oxide based RRAM'20117,943,920'Resistive memory structure with buffer layer'20117,924,600'Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states'20117,923,285'Method for forming self-aligned thermal isolation cell for a variable resistance memory array'20117,881,123'Multi-operation mode nonvolatile memory'20117,881,112'Program and erase methods with substrate transient hot carrier injections in a non-volatile memory'20117,820,997'Resistor random access memory cell with reduced active area and reduced contact areas'20107,816,661'Air cell thermal isolation for a memory array formed of a programmable resistive material'20107,777,215'Resistive memory structure with buffer layer'20107,763,935'ONO formation of semiconductor memory device and method of fabricating the same'20107,755,153'Structure and method for a magnetic memory device with proximity writing'20107,732,800'Resistor random access memory cell with L-shaped electrode'20107,718,989'Resistor random access memory cell device'20107,709,334'Stacked non-volatile memory device and methods for fabricating the same'20107,704,865'Methods of forming charge-trapping dielectric layers for semiconductor memory devices'20107,697,316'Multi-level cell resistance random access memory with metal oxides'20107,688,615'Magnetic random access memory, manufacturing method and programming method thereof'20107,684,234'Methods and apparatus for thermally assisted programming of a magnetic memory device'20107,667,293'Resistive random access memory and method for manufacturing the same'20107,616,472'Method and apparatus for non-volatile multi-bit memory'20097,608,848'Bridge resistance random access memory device with a singular contact structure'20097,605,079'Manufacturing method for phase change RAM with electrode layer process'20097,599,217'Memory cell device and manufacturing method'20097,595,218'Programmable resistive RAM and manufacturing method'20097,590,005'Program and erase methods with substrate transient hot carrier injections in a non-volatile memory'20097,586,778'Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states'20097,560,337'Programmable resistive RAM and manufacturing method'20097,560,762'Asymmetric floating gate NAND flash memory'20097,554,144'Memory device and manufacturing method'20097,531,825'Method for forming self-aligned thermal isolation cell for a variable resistance memory array'20097,527,985'Method for manufacturing a resistor random access memory with reduced active area and reduced contact areas'20097,524,722'Resistance type memory device and fabricating method and operating method thereof'20097,473,589'Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same'20097,457,149'Methods and apparatus for thermally assisted programming of a magnetic memory device'20087,450,423'Methods of operating non-volatile memory cells having an oxide/nitride multilayer insulating structure'20087,442,603'Self-aligned structure and method for confining a melting point in a resistor random access memory'20087,414,282'Method of manufacturing a non-volatile memory device'20087,388,771'Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states'20087,352,613'Magnetic memory device and methods for making a magnetic memory device'20087,209,390'Operation scheme for spectrum shift in charge trapping non-volatile memory'20077,200,045'Method for programming a charge-trapping nonvolatile memory cell by raised-Vs channel initialed secondary electron injection (CHISEL)'20077,075,828'Operation scheme with charge balancing erase for charge trapping non-volatile memory'20066,927,136'Non-volatile memory cell having metal nano-particles for trapping charges and fabrication thereof'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2016Patents assigned to MACRONIX INT CO LTD (82)· patent assignee history
2005–2016Based in Hsinchu, TW· patent location history
2006–2010Based in Jubei, TW· patent location history
2008–2015Based in Jhubei City, TW· patent location history
2008–2014Based in Hsin Chu, TW· patent location history
2009–2012Based in Ju Bai, TW· patent location history
2011–2015Patents assigned to LAI ERH-KUN (23)· patent assignee history
2011–2016Patents assigned to HSIEH KUANG YEU (16)· patent assignee history
2011–2015Patents assigned to HSIEH KUANG-YEU (13)· patent assignee history
2011–2015Patents assigned to HO CHIAHUA (12)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MACRONIX INT CO LTD | 82 | 2005–2016 |
| LAI ERH-KUN | 23 | 2011–2015 |
| HSIEH KUANG YEUself | 16 | 2011–2016 |
| HSIEH KUANG-YEUself | 13 | 2011–2015 |
| HO CHIAHUA | 12 | 2011–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 49 | 2005–2016 |
| Jhubei City, TW | 15 | 2008–2015 |
| Hsin Chu, TW | 9 | 2008–2014 |
| Ju Bai, TW | 6 | 2009–2012 |
| Jubei, TW | 3 | 2006–2010 |