Inventor
Larry Wang
Inventor
San Jose, CA, US
Overview
Patents· 42 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1032%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H10DInorganic electric semiconductor devices15%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests9%
G11CStatic stores6%
H01LSemiconductor devices4%
H10BElectronic memory devices4%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
G06FElectric digital data processing3%
B82YSpecific uses or applications of nanostructures1%
PatentTitleYear
10,997,040System and method for weight based data protection202110,623,192Gate oxide breakdown in OTP memory cells for physical unclonable function (PUF) security202010,163,520OTP cell with improved programmability201810,032,522Three-transistor OTP memory cell20189,224,714'Semiconductor device having a through-substrate via'20159,129,710'Dynamic trim method for non volatile memory products'20158,748,232'Semiconductor device having a through-substrate via'20148,630,137'Dynamic trim method for non-volatile memory products'20146,962,842'Method of removing a sacrificial emitter feature in a BICMOS process with a super self-aligned BJT'20056,599,810'Shallow trench isolation formation with ion implantation'20036,530,997'Use of gaseous silicon hydrides as a reducing agent to remove re-sputtered silicon oxide'20036,383,906'Method of forming junction-leakage free metal salicide in a semiconductor wafer with ultra-low silicon consumption'20026,380,047'Shallow trench isolation formation with two source/drain masks and simplified planarization mask'20026,380,040'Prevention of dopant out-diffusion during silicidation and junction formation'20026,323,516'Flash memory device and fabrication method having a high coupling ratio'20016,265,273'Method of forming rectangular shaped spacers'20016,239,031'Stepper alignment mark structure for maintaining alignment integrity'20016,238,986'Formation of junctions by diffusion from a doped film at silicidation'20016,232,635'Method to fabricate a high coupling flash cell with less silicide seam problem'20016,171,962'Shallow trench isolation formation without planarization mask'20016,169,005'Formation of junctions by diffusion from a doped amorphous silicon film during silicidation'20016,162,699'Method for generating limited isolation trench width structures and a device having a narrow isolation trench surrounding its periphery'20006,162,689'Multi-depth junction formation tailored to silicide formation'20006,150,243'Shallow junction formation by out-diffusion from a doped dielectric layer through a salicide layer'20006,143,624'Shallow trench isolation formation with spacer-assisted ion implantation'20006,130,467'Shallow trench isolation with spacers for improved gate oxide quality'20006,124,183'Shallow trench isolation formation with simplified reverse planarization mask'20006,100,145'Silicidation with silicon buffer layer and silicon spacers'20006,096,599'Formation of junctions by diffusion from a doped film into and through a silicide during silicidation'20006,090,712'Shallow trench isolation formation with no polish stop'20006,090,713'Shallow trench isolation formation with simplified reverse planarization mask'20006,087,243'Method of forming trench isolation with high integrity, ultra thin gate oxide'20006,074,927'Shallow trench isolation formation with trench wall spacer'20006,037,671'Stepper alignment mark structure for maintaining alignment integrity'20005,970,363'Shallow trench isolation formation with improved trench edge oxide'19995,970,362'Simplified shallow trench isolation formation with no polish stop'19995,963,816'Method for making shallow trench marks'19995,930,645'Shallow trench isolation formation with reduced polish stop thickness'19995,926,723'Generation of a loose planarization mask having relaxed boundary conditions for use in shallow trench isolation processes'19995,904,543'Method for formation of offset trench isolation by the use of disposable spacer and trench oxidation'19995,893,744'Method of forming a zero layer mark for alignment in integrated circuit manufacturing process employing shallow trench isolation'19995,485,097'Method of electrically measuring a thin oxide thickness by tunnel voltage'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996–2003Patents assigned to ADVANCED MICRO DEVICES INC (33)· patent assignee history
1996–2020Based in San Jose, CA, US· patent location history
2005–2015Patents assigned to MAXIM INTEGRATED PRODUCTS (5)· patent assignee history
2014Patents assigned to BERGEMONT ALBERT (1)· patent assignee history
2014Patents assigned to CHEN CHE-PING (1)· patent assignee history
2018–2020Patents assigned to SYNOPSYS INC (3)· patent assignee history
2021Based in Chengdu, CN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 33 | 1996–2003 |
| MAXIM INTEGRATED PRODUCTS | 5 | 2005–2015 |
| SYNOPSYS INC | 3 | 2018–2020 |
| BERGEMONT ALBERT | 1 | 2014 |
| CHEN CHE-PING | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 41 | 1996–2020 |
| Chengdu, CN | 1 | 2021 |