Inventor
Qwai H. Low
Inventor
Cupertino, CA, US
Overview
Patents· 47 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1064%
Y10TTechnical subjects covered by former us classification9%
H01LSemiconductor devices8%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
F02FCylinders, pistons or casings, for combustion engines4%
G01RMeasuring electric variables3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
H05KPrinted circuits1%
PatentTitleYear
11,031,3623D-interconnect202110,181,4473D-interconnect20199,875,955Low cost hybrid high density package20189,508,687'Low cost hybrid high density package'20168,963,310'Low cost hybrid high density package'20158,869,389'Method of manufacturing an electronic device package'20148,525,309'Flip-chip QFN structure using etched lead frame'20138,525,312'Area array quad flat no-lead (QFN) package'20138,384,205'Electronic device package and method of manufacture'20138,350,379'Package with power and ground through via'20138,334,467'Lead frame design to improve reliability'20128,134,232'Heat dissipation for integrated circuit'20128,125,091'Wire bonding over active circuits'20127,993,981'Electronic device package and method of manufacture'20117,531,442'Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing'20097,420,809'Heat spreader in integrated circuit package'20087,235,889'Integrated heatspreader for use in wire bonded ball grid array semiconductor packages'20076,998,638'Test structure for detecting bonding-induced cracks'20066,963,138'Dielectric stack'20056,861,343'Buffer metal layer'20056,861,748'Test structure'20056,825,563'Slotted bonding pad'20046,798,035'Bonding pad for low k dielectric'20046,781,150'Test structure for detecting bonding-induced cracks'20046,743,979'Bonding pad isolation'20046,603,200'Integrated circuit package'20036,573,113'Integrated circuit having dedicated probe pads for use in testing densely patterned bonding pads'20036,489,571'Molded tape ball grid array package'20026,486,002'Tape design to reduce warpage'20026,429,534'Interposer tape for semiconductor package'20026,425,179'Method for assembling tape ball grid arrays'20026,329,278'Multiple row wire bonding with ball bonds of outer bond pads bonded on the leads'20016,285,077'Multiple layer tape ball grid array package'20016,143,586'Electrostatic protected substrate'20006,114,189'Molded array integrated circuit package'20006,057,594'High power dissipating tape ball grid array package'20006,040,632'Multiple sized die'20005,973,393'Apparatus and method for stackable molded lead frame ball grid array packaging of integrated circuits'19995,973,397'Semiconductor device and fabrication method which advantageously combine wire bonding and tab techniques to increase integrated circuit I/O pad density'19995,923,047'Semiconductor die having sacrificial bond pads for die test'19995,886,398'Molded laminate package with integral mold gate'19995,841,191'Ball grid array package employing raised metal contact rings'19985,814,881'Stacked integrated chip package and method of making same'19985,568,683'Method of cooling a packaged electronic device'19965,463,529'High power dissipating packages with matched heatspreader heatsink assemblies'19955,386,144'Snap on heat sink attachment'19955,353,193'High power dissipating packages with matched heatspreader heatsink assemblies'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–2006Patents assigned to LSI LOGIC CORP (29)· patent assignee history
1994–2021Based in Cupertino, CA, US· patent location history
2007–2014Patents assigned to LSI CORP (10)· patent assignee history
2012–2015Patents assigned to LOW QWAI H (5)· patent assignee history
2013–2018Patents assigned to TESSERA INC (5)· patent assignee history
2013–2015Patents assigned to DESAI Kishor (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LSI LOGIC CORP | 29 | 1994–2006 |
| LSI CORP | 10 | 2007–2014 |
| LOW QWAI Hself | 5 | 2012–2015 |
| TESSERA INC | 5 | 2013–2018 |
| DESAI Kishor | 3 | 2013–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cupertino, California, US | 47 | 1994–2021 |