Inventor
Scott Te-Sheng Lien
Inventor
Palo Alto, CA, US
Overview
Patents· 9 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique70%
G06FElectric digital data processing30%
PatentTitleYear
8,145,923'Circuit for and method of minimizing power consumption in an integrated circuit device'20127,786,782'Method and apparatus for counter-based clock signal adaptation'20107,620,929'Programmable logic device having a programmable selector circuit'20097,398,487'Programmable logic device-structured application specific integrated circuit'20087,397,273'Bidirectional logic isolation multiplexing with voltage level translation capability for open-drain circuitry'20087,345,508'Programmable logic device having a programmable selector circuit'20087,129,747'CPLD with fast logic sharing between function blocks'20066,989,690'Methods of implementing scalable routing matrices for programmable logic devices'20066,981,232'Method and system for integrating a program and a processor into an application specific processor'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2012Patents assigned to XILINX INC (9)· patent assignee history
2005–2012Based in Palo Alto, CA, US· patent location history
2012Patents assigned to JANG TETSE (1)· patent assignee history
2012Patents assigned to JENKINS IV JESSE H (1)· patent assignee history
2012Patents assigned to LAKKAPRAGADA SHANKAR (1)· patent assignee history
2012Patents assigned to LIEN SCOTT TE-SHENG (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| XILINX INC | 9 | 2005–2012 |
| JANG TETSE | 1 | 2012 |
| JENKINS IV JESSE H | 1 | 2012 |
| LAKKAPRAGADA SHANKAR | 1 | 2012 |
| LIEN SCOTT TE-SHENGself | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Palo Alto, California, US | 9 | 2005–2012 |