Inventor

Wen-Hann Wang

Inventor

Portland, OR, US

Overview

19→

Patents

1996–2014

Patent span

Physics

Primary field (CPC G)

Patents· 19 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing100%

PatentTitleYear

8,745,306'Scalable distributed memory and I/O multiprocessor system'2014 8,255,605'Scalable distributed memory and I/O multiprocessor system'2012 7,930,464'Scalable memory and I/O multiprocessor systems'2011 7,603,508'Scalable distributed memory and I/O multiprocessor systems and associated methods'2009 7,343,442'Scalable distributed memory and I/O multiprocessor systems and associated methods'2008 7,076,613'Cache line pre-load and pre-own based on cache coherence speculation'2006 7,058,750'Scalable distributed memory and I/O multiprocessor system'2006 6,725,341'Cache line pre-load and pre-own based on cache coherence speculation'2004 6,006,299'Apparatus and method for caching lock conditions in a multi-processor system'1999 5,956,746'Computer system having tag information in a processor and cache memory'1999 5,829,038'Backward inquiry to lower level caches prior to the eviction of a modified line from a higher level cache in a microprocessor hierarchical cache structure'1998 5,809,524'Method and apparatus for cache memory replacement line identification'1998 5,715,428'Apparatus for maintaining multilevel cache hierarchy coherency in a multiprocessor computer system'1998 5,701,503'Method and apparatus for transferring information between a processor and a memory system'1997 5,642,494'Cache memory with reduced request-blocking'1997 5,619,673'Virtual access cache protection bits handling method and apparatus'1997 5,551,005'Apparatus and method of handling race conditions in mesi-based multiprocessor system with private caches'1996 5,548,742'Method and apparatus for combining a direct-mapped cache and a multiple-way cache in a cache memory'1996 5,530,832'System and method for practicing essential inclusion in a multiprocessor and cache hierarchy'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–2014Patents assigned to INTEL CORP (18)· patent assignee history

1996–2014Based in Portland, OR, US· patent location history

2012–2014Patents assigned to BORKAR NITIN Y (2)· patent assignee history

2012–2014Patents assigned to CHENG KAI (2)· patent assignee history

2012–2014Patents assigned to DERMER GREGORY E (2)· patent assignee history

2012–2014Patents assigned to HOFSHEIER RICHARD H (2)· patent assignee history

2012Based in Shanghai, CN· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	18	1996–2014
BORKAR NITIN Y	2	2012–2014
CHENG KAI	2	2012–2014
DERMER GREGORY E	2	2012–2014
HOFSHEIER RICHARD H	2	2012–2014

Locations

Location	Patents	Span
Portland, OR, US	18	1996–2014
Shanghai, CN	1	2012