Inventor

Yanru Li

Inventor
San Diego, CA, US

Overview

38→
Patents
2016–2021
Patent span
Physics
Primary field (CPC G)

Patents· 38 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing37%
G11CStatic stores23%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use17%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications5%
H01LSemiconductor devices2%
H03MCoding2%
B60KArrangement or mounting of propulsion units or of transmissions in vehicles1%
B60LPropulsion of electrically-propelled vehicles1%
B60YIndexing scheme relating to aspects cross-cutting vehicle technology1%
G05BControl or regulating systems in general1%
PatentTitleYear
11,069,290Display substrate, fabrication method of the display substrate and display apparatus202110,878,880Selective volatile memory refresh via memory-side data valid indication202010,831,658Read-with-invalidate modified data in a cache line in a cache memory202010,817,224Preemptive decompression scheduling for a NAND storage device202010,795,830Write access control for double data rate write-x/datacopy0 commands202010,780,795Battery heating system and control method thereof202010,783,252System and method for booting within a heterogeneous memory environment202010,726,904Partial refresh technique to save memory refresh power202010,642,781Boot time determination of calibration parameters for a component coupled to a system-on-chip202010,599,442Selectable boot CPU202010,591,975Memory access management for low-power use cases of a system on chip via secure non-volatile random access memory202010,579,516Systems and methods for providing power-efficient file system operation to a non-volatile block memory202010,482,943Systems and methods for improved error correction in a refreshable memory201910,387,333Non-volatile random access memory with gated security access201910,338,837Dynamic mapping of applications on NVRAM/DRAM hybrid memory201910,332,582Partial refresh technique to save memory refresh power201910,310,757Systems and methods for memory power saving via kernel steering to memory balloons201910,180,908Method and apparatus for virtualized control of a shared system cache201910,157,008Systems and methods for optimizing memory power consumption in a heterogeneous system memory201810,089,238Method and apparatus for a shared cache with dynamic partitioning201810,090,040Systems and methods for reducing memory power consumption via pre-filled DRAM values20189,983,930Systems and methods for implementing error correcting code regions in a memory20189,928,924'Systems, methods, and computer programs for resolving dram defects'20189,823,846'Systems and methods for expanding memory for a system on chip'20179,824,046'Using USB signaling to trigger a device to enter a mode of operation'20179,812,222'Method and apparatus for in-system management and repair of semi-conductor memory failure'20179,785,371'Power-reducing memory subsystem having a system cache and local resource management'20179,779,798'Systems, methods, and computer programs for providing row tamper protection in a multi-bank memory cell array'20179,778,871'Power-reducing memory subsystem having a system cache and local resource management'20179,734,073'System and method for flash read cache with adaptive pre-fetch'20179,632,562'Systems and methods for reducing volatile memory standby power in a portable computing device'20179,612,648'System and method for memory channel interleaving with selective power or performance optimization'20179,507,675'Systems and methods for recovering from uncorrected DRAM bit errors'20169,495,261'Systems and methods for reducing memory failures'20169,472,261'Systems and methods to refresh DRAM based on temperature and based on calibration data'20169,431,077'Dual host embedded shared device controller'20169,418,033'Using USB signaling to trigger a device to enter a mode of operation'20169,299,457'Kernel masking of DRAM defects'2016

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2016–2020Patents assigned to QUALCOMM INC (35)· patent assignee history
2016–2020Based in San Diego, CA, US· patent location history
2020Patents assigned to CONTEMPORARY AMPEREX TECHNOLOGY CO LTD (1)· patent assignee history
2020Patents assigned to INTEL CORP (1)· patent assignee history
2020Based in Ningde, CN· patent location history
2021Patents assigned to BOE TECHNOLOGY GROUP CO LTD (1)· patent assignee history
2021Patents assigned to CHENGDU BOE OPTOELECT TECH CO (1)· patent assignee history
2021Based in Beijing, CN· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
QUALCOMM INC352016–2020
BOE TECHNOLOGY GROUP CO LTD12021
CHENGDU BOE OPTOELECT TECH CO12021
CONTEMPORARY AMPEREX TECHNOLOGY CO LTD12020
INTEL CORP12020
Locations
LocationPatentsSpan
San Diego, California, US362016–2020
Beijing, CN12021
Ningde, CN12020