Inventor

Patrick W. Bosshart

Inventor

Plano, TX, US

Overview

1988–2021

Patent span

Physics

Primary field (CPC G)

Patents· 140 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing39%

H04LTransmission of digital information, e.g. telegraphic communication27%

G11CStatic stores13%

H03KPulse technique7%

H10DInorganic electric semiconductor devices4%

H10BElectronic memory devices2%

G06NComputing arrangements based on specific computational models1%

H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses1%

H04QSelecting1%

B60WConjoint control of vehicle sub-units of different type or different function1%

PatentTitleYear

10,967,872Methods and systems for presenting collected driving data2021 10,877,838Data plane error detection for ternary content-addressable memory (TCAM) of a forwarding element2020 10,873,534Data plane with flow learning circuit2020 10,826,840Multiple copies of stateful tables2020 10,805,437Compiler and hardware interactions to remove action dependencies in the data plane of a network forwarding element2020 10,785,151Packet processing match and action pipeline structure with dependency calculation removing false dependencies2020 10,771,387Multiple packet data container types for a processing pipeline2020 10,771,401Forwarding element data plane with computing parameter distributor2020 10,764,200Openflow match and action pipeline structure2020 10,764,176Compiler and hardware interactions to reuse register fields in the data plane of a network forwarding element2020 10,721,188Forwarding element data plane with computing parameter distributor2020 10,721,167Runtime sharing of unit memories between match tables in a network forwarding element2020 10,712,961Addressing match and action entries in a match-action stage2020 10,671,304Coding scheme for indirect addressing of multiple action memories2020 10,645,032Packet processing match and action unit with stateful actions2020 10,616,101Forwarding element with flow learning circuit in its data plane2020 10,601,732Configurable packet processing pipeline for handling non-packet data2020 10,594,630Expansion of packet data within processing pipeline2020 10,515,699Error handling for match action unit memory of a forwarding element2019 10,511,523Network forwarding element with data plane packet snapshotting capabilities2019 10,467,217Loop detection in cuckoo hashtables2019 10,454,833Pipeline chaining2019 10,430,095Dynamic memory reallocation for match-action packet processing2019 10,432,527Packet header field extraction2019 10,372,365Virtual addresses for action memories of a hardware forwarding element2019 10,333,847Packet processing match and action unit with a VLIW action engine2019 10,318,587Algorithmic TCAM based ternary lookup2019 10,313,495Compiler and hardware interactions to remove action dependencies in the data plane of a network forwarding element2019 10,313,231Resilient hashing for forwarding packets2019 10,303,544Data plane error detection for ternary content-addressable memory (TCAM) of a forwarding element2019 10,303,387Coding scheme for indirect addressing of multiple action memories2019 10,268,634Proxy hash table2019 10,225,381Configuring a switch for extracting packet header fields2019 10,133,499Coding scheme for identifying location of action entries2018 10,127,983Error handling for match action unit memory of a forwarding element2018 10,104,004Openflow match and action pipeline structure2018 10,078,463Dynamic memory reallocation for match-action packet processing2018 10,067,967Hash table storing reduced search key2018 10,063,479Fast adjusting load balancer2018 10,033,626Conditional instructions for packet processing2018 10,009,276Packet processing match and action unit with a VLIW action engine2018 9,998,574Packet processing match and action unit with configurable bit allocation2018 9,940,056Coding scheme for identifying location of action entries2018 9,910,615'Coding scheme for indirect addressing of multiple action memories'2018 9,912,610'Data-plane stateful processing units in packet processing pipelines'2018 9,906,445'Packet processing match and action pipeline structure with dependency calculation removing false dependencies'2018 9,880,768'Dynamic memory reallocation for match-action packet processing'2018 9,826,067'Packet processing match and action unit with configurable bit allocation'2017 9,826,071'Configuring a switch for extracting packet header fields'2017 9,825,862'Packet header field extraction'2017 9,712,439'Packet processing match and action unit with configurable memory allocation'2017 9,646,105'Reduced complexity hashing'2017 9,544,231'Packet processing VLIW action unit with OR-multi-ported instruction memory'2017 9,529,531'Proxy hash table'2016 9,484,095'TCAM providing efficient move contents operation'2016 9,419,903'Structure for implementing openflow all group buckets using egress flow table entries'2016 9,313,124'Conditional instructions for packet processing'2016 9,313,127'Rotate-mask-merge and deposit-field instructions for packet processing'2016 9,258,224'Packet processing VLIW action unit with or-multi-ported instruction memory'2016 9,087,585'TCAM with efficient range search capability'2015 9,087,586'TCAM with efficient multiple dimension range search capability'2015 8,874,876'Method and apparatus for packet switching'2014 8,650,529'System and method for integrated circuit layout editing with asymmetric zoom views'2014 8,510,702'Interactive routing editor with symbolic and geometric views for integrated circuit layout'2013 8,473,891'System and method for integrated circuit layout editing using reference frames'2013 8,193,832'Arbiter array using two-dimensional address decoding'2012 8,131,791'Decision feedback equalizer having parallel processing architecture'2012 8,125,810'Low power ternary content-addressable memory (TCAM)'2012 8,050,903'Apparatus and method for checkpointing simulation data in a simulator'2011 7,859,024'Integrated circuit having efficiently packed decoupling capacitors'2010 7,709,301'Integrated circuit having efficiently packed decoupling capacitors'2010 7,683,688'High performance clocked latches and devices therefrom'2010 7,409,415'Processor system with efficient shift operations including EXTRACT operation'2008 7,349,934'Processor system and method with combined data left and right shift operation'2008 7,315,540'Random access memory based space time switch architecture'2008 7,216,247'Methods and systems to reduce data skew in FIFOs'2007 7,062,635'Processor system and method providing data to selected sub-units in a processor functional unit'2006 6,978,387'Hold time latch with decreased percharge node voltage leakage'2005 6,970,967'Crossbar circuit having a plurality of repeaters forming different repeater arrangements'2005 6,910,123'Processor with conditional instruction execution based upon state of corresponding annul bit of annul code'2005 6,791,365'Dynamic logic circuits using transistors having differing threshold voltages and delayed low threshold voltage leakage protection'2004 6,703,884'System and method for distributing a reference clock in an integrated circuit using filtered power supply line'2004 6,657,484'System and method for decoupling capacitance for an integrated circuit chip'2003 6,553,547'Method and system for generating charge sharing test vectors'2003 6,430,684'Processor circuits, systems, and methods with efficient granularity shift and/or merge instruction(s)'2002 6,366,941'Multi-dimensional Galois field multiplier'2002 6,344,759'Hybrid data and clock recharging techniques in domino logic circuits minimizes charge sharing during evaluation'2002 6,338,137'Data processor having memory access unit with predetermined number of instruction cycles between activation and initial data transfer'2002 6,327,218'Integrated circuit time delay measurement apparatus'2001 6,304,123'Data storage circuits using a low threshold voltage output enable circuit'2001 6,279,077'Bus interface buffer control in a microprocessor'2001 6,261,879'Differential SOI amplifiers having tied floating body connections'2001 6,246,266'Dynamic logic circuits using selected transistors connected to absolute voltages and additional selected transistors connected to selectively disabled voltages'2001 6,242,952'Inverting hold time latch circuits, systems, and methods'2001 6,231,147'Data storage circuits using a low threshold voltage output enable circuit'2001 6,223,248'Circuits systems and methods for re-mapping memory row redundancy during two cycle cache access'2001 6,177,300'Memory with storage cells having SOI drive and access transistors with tied floating body connections'2001 6,078,634'Phase-locked loop circuit with a multi-cycle phase detector and multi-current charge pump'2000 6,065,146'Error correcting memory'2000 6,055,204'Circuits, systems, and methods for re-mapping memory column redundancy'2000 6,049,672'Microprocessor with circuits, systems, and methods for operating with patch micro-operation codes and patch microinstruction codes stored in multi-purpose memory structure'2000 6,049,231'Dynamic multiplexer circuits, systems, and methods having three signal inversions from input to output'2000 6,040,716'Domino logic circuits, systems, and methods with precharge control based on completion of evaluation by the subsequent domino logic stage'2000 6,037,808'Differential SOI amplifiers having tied floating body connections'2000 6,021,087'Dynamic logic memory addressing circuits, systems, and methods with decoder fan out greater than 2:1'2000 6,009,037'Dynamic logic memory addressing circuits, systems, and methods with reduced capacitively loaded predecoders'1999 5,982,702'Dynamic logic memory addressing circuits, systems, and methods with predecoders providing data and precharge control to decoders'1999 5,954,812'Apparatus for caching system management memory in a computer having a system management mode employing address translation'1999 5,943,258'Memory with storage cells having SOI drive and access transistors with tied floating body connections'1999 5,905,680'Self-timed comparison circuits and systems'1999 5,896,305'Shifter circuit for an arithmetic logic unit in a microprocessor'1999 5,831,451'Dynamic logic circuits using transistors having differing threshold voltages'1998 5,821,778'Using cascode transistors having low threshold voltages'1998 5,815,697'Circuits, systems, and methods for reducing microprogram memory power for multiway branching'1998 5,815,005'Power reduction circuits and systems for dynamic logic gates'1998 5,796,995'Circuit and method for translating signals between clock domains in a microprocessor'1998 5,732,236'Circuit and method for controlling access to paged DRAM banks with request prioritization and improved precharge schedule'1998 5,629,859'Method for timing-directed circuit optimizations'1997 5,604,889'Memory management system for checkpointed logic simulator with increased locality of data'1997 5,604,894'Memory management system for checkpointed logic simulator with increased locality of data'1997 5,600,583'Circuit and method for detecting if a sum of two multidigit numbers equals a third multidigit number prior to availability of the sum'1997 5,588,127'High speed microprocessor branch decision circuit'1996 5,508,950'Circuit and method for detecting if a sum of two multibit numbers equals a third multibit constant number prior to availability of the sum'1996 5,504,867'High speed microprocessor branch decision circuit'1996 5,461,577'Comprehensive logic circuit layout system'1995 5,455,929'Logic simulator employing hierarchical checkpointing'1995 5,442,325'Voltage-controlled oscillator and system with reduced sensitivity to power supply variation'1995 5,440,717'Computer pipeline including dual-ported, content-addressable writebuffer'1995 5,386,527'Method and system for high-speed virtual-to-physical address translation and cache tag matching'1995 5,270,955'Method of detecting arithmetic or logical computation result'1993 5,235,686'Computer system having mixed macrocode and microcode'1993 5,150,309'Comprehensive logic circuit layout system'1992 5,119,313'Comprehensive logic circuit layout system'1992 5,019,888'Circuit to improve electrostatic discharge protection'1991 5,015,882'Compound domino CMOS circuit'1991 4,991,081'Cache memory addressable by both physical and virtual addresses'1991 4,980,860'Cross-coupled complementary bit lines for a semiconductor memory with pull-up circuitry'1990 4,870,598'Comprehensive logic circuit layout system'1989 4,815,019'Fast ALU equals zero circuit'1989 4,754,421'Multiple precision multiplication device'1988

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1988–2020Patents assigned to TEXAS INSTRUMENTS INC (99)· patent assignee history

1988–2011Based in Dallas, TX, US· patent location history

1993–2020Based in Plano, TX, US· patent location history

2012–2014Patents assigned to BOSSHART PATRICK W (7)· patent assignee history

2014Patents assigned to BHADRA SANDEEP (1)· patent assignee history

2014Patents assigned to KIM HUN-SEOK (1)· patent assignee history

2016–2020Patents assigned to BAREFOOT NETWORKS INC (39)· patent assignee history

2021Based in Cambridge, MA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TEXAS INSTRUMENTS INC	99	1988–2020
BAREFOOT NETWORKS INC	39	2016–2020
BOSSHART PATRICK Wself	7	2012–2014
BHADRA SANDEEP	1	2014
KIM HUN-SEOK	1	2014

Locations

Location	Patents	Span
Plano, Texas, US	126	1993–2020
Dallas, Texas, US	13	1988–2011
Cambridge, Massachusetts, US	1	2021