Inventor
Shunhua T. Chang
Inventor
South Burlington, VT, US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices46%
G01RMeasuring electric variables15%
H01LSemiconductor devices10%
H02HEmergency protective circuit arrangements10%
H05KPrinted circuits8%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
G06FElectric digital data processing3%
G09GArrangements or circuits for control of indicating devices using static means to present variable information3%
PatentTitleYear
10,636,872Apparatus and method to prevent integrated circuit from entering latch-up mode202010,359,461Integrated circuit protection during high-current ESD testing20199,869,708'Integrated circuit protection during high-current ESD testing'20189,684,029'Transmission line pulse and very fast transmission line pulse reflection control'20179,435,841'Integrated circuit protection during high-current ESD testing'20169,377,496'Cancellation of secondary reverse reflections in a very-fast transmission line pulse system'20169,274,155'Cancellation of secondary reverse reflections in a very-fast transmission line pulse system'20168,803,276'Electrostatic discharge (ESD) device and method of fabricating'20148,796,731'Low leakage, low capacitance electrostatic discharge (ESD) silicon controlled recitifer (SCR), methods of manufacture and design structure'20148,760,827'Robust ESD protection circuit, method and design structure for tolerant and failsafe designs'20148,730,624'Electrostatic discharge power clamp with a JFET based RC trigger circuit'20148,634,172'Silicon controlled rectifier based electrostatic discharge protection circuit with integrated JFETs, method of operation and design structure'20148,614,489'Vertical NPNP structure in a triple well CMOS process'20138,597,993'Electrostatic discharge (ESD) device and method of fabricating'20138,513,738'ESD field-effect transistor and integrated diffusion resistor'20138,363,367'Electrical overstress protection circuit'20138,354,722'SCR/MOS clamp for ESD protection of integrated circuits'20138,350,329'Low trigger voltage electrostatic discharge NFET in triple well CMOS technology'20138,299,533'Vertical NPNP structure in a triple well CMOS process'20128,169,760'Signal and power supply integrated ESD protection device'20127,648,869'Method of fabricating semiconductor structures for latch-up suppression'20107,385,275'Shallow trench isolation method for shielding trapped charge in a semiconductor device'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2019Patents assigned to IBM (21)· patent assignee history
2008–2020Based in South Burlington, VT, US· patent location history
2012–2016Patents assigned to GAUTHIER JR ROBERT J (13)· patent assignee history
2012–2014Patents assigned to CHATTY KIRAN V (12)· patent assignee history
2012–2014Patents assigned to MUHAMMAD MUJAHID (12)· patent assignee history
2012–2014Patents assigned to LI JUNJUN (9)· patent assignee history
2016Based in Essex Junction, VT, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 21 | 2008–2019 |
| GAUTHIER JR ROBERT J | 13 | 2012–2016 |
| CHATTY KIRAN V | 12 | 2012–2014 |
| MUHAMMAD MUJAHID | 12 | 2012–2014 |
| LI JUNJUN | 9 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| South Burlington, VT, US | 21 | 2008–2020 |
| Essex Junction, VT, US | 1 | 2016 |