Inventor
Paul S. Andry
Inventor
Yorktown Heights, NY, US
Overview
Patents· 115 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1022%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H01LSemiconductor devices10%
H10DInorganic electric semiconductor devices6%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution5%
Y02PClimate change mitigation technologies in the production or processing of goods5%
Y10TTechnical subjects covered by former us classification5%
H01MProcesses or means, e.g. batteries, for the direct conversion of chemical energy into electrical energy4%
H05KPrinted circuits3%
G01RMeasuring electric variables2%
PatentTitleYear
11,127,715Large channel interconnects with through silicon Vias (TSVs) and method for constructing the same202111,121,005Handler bonding and debonding for semiconductor dies202111,043,690Sandwich-parallel micro-battery202110,686,164Cathode for thin film microbattery202010,687,425Method of forming a plurality of electro-optical module assemblies202010,679,887Handler bonding and debonding for semiconductor dies202010,670,656Integrated electro-optical module assembly202010,638,613Method of forming a plurality of electro-optical module assemblies202010,622,590Method of forming a homogeneous solid metallic anode for a thin film microbattery202010,586,726Handler bonding and debonding for semiconductor dies202010,581,037Low-profile battery construct with engineered interfaces202010,573,538Handler bonding and debonding for semiconductor dies202010,431,828Microbattery with through-silicon via electrodes201910,393,798Integrated electro-optical module assembly201910,388,929Microbattery separator201910,381,255Double layer release temporary bond and debond processes and systems201910,347,588Thin 3D die with electromagnetic radiation blocking encapsulation201910,325,785Handler bonding and debonding for semiconductor dies201910,297,876Micro battery design and diagnosis201910,280,077Flexible electronics for wearable healthcare sensors201910,224,229Double layer release temporary bond and debond processes and systems201910,224,219Handler bonding and debonding for semiconductor dies201910,177,116Large channel interconnects with through silicon vias (TSVs) and method for constructing the same201910,166,632In-situ laser beam position and spot size sensor and high speed scanner calibration, wafer debonding method201910,162,013Micro battery design and diagnosis201810,118,250In-situ laser beam position and spot size sensor and high speed scanner calibration, wafer debonding method201810,096,802Homogeneous solid metallic anode for thin film microbattery201810,079,375Dual seal microbattery and method of making201810,069,116Cathode for thin film microbattery201810,056,337Thin 3D die with electromagnetic radiation blocking encapsulation20189,953,501Methods of forming microelectronic smart tags20189,947,570Handler bonding and debonding for semiconductor dies20189,941,788Three-D power converter in three distinct strata20189,876,200All-silicon hermetic package and processing for narrow, low-profile microbatteries20189,822,002'Flexible electronics for wearable healthcare sensors'20179,806,299'Cathode for thin film microbattery'20179,748,131'Low temperature adhesive resins for wafer bonding'20179,684,862'Microelectronic smart tags'20179,660,525'Three-D power converter in three distinct strata'20179,620,824'Micro battery design and diagnosis'20179,601,364'Low temperature adhesive resins for wafer bonding'20179,520,779'Three-D power converter in three distinct strata'20169,508,566'Wafer level overmold for three dimensional surfaces'20169,472,789'Thin, flexible microsystem with integrated energy source'20169,418,895'Dies for RFID devices and sensor applications'20169,412,663'Dies for RFID devices and sensor applications'20169,362,223'Integrated circuit assembly with cushion polymer layer'20169,331,141'CMOS structure on replacement substrate'20169,324,601'Low temperature adhesive resins for wafer bonding'20169,312,761'Three-D power converter in three distinct strata'20169,299,665'Formation of alpha particle shields in chip packaging'20169,209,128'Integrated circuit assembly with cushion polymer layer'20159,200,883'Transferable probe tips'20159,159,602'Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers'20159,059,161'Composite wiring board with electrical through connections'20159,029,238'Advanced handler wafer bonding and debonding'20158,928,145'Formation of alpha particle shields in chip packaging'20158,855,452'Silicon photonic chip optical coupling structures'20148,735,251'Through silicon via and method of fabricating same'20148,658,535'Optimized annular copper TSV'20148,637,937'Through silicon via for use in integrated circuit chips'20148,592,932'Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers'20138,564,113'Electrostatic chucking of an insulator handle substrate'20138,559,474'Silicon carrier optoelectronic packaging'20138,487,425'Optimized annular copper TSV'20138,440,544'CMOS structure and method of manufacture'20138,388,782'Handler attachment for integrated circuit fabrication'20138,354,737'Small area, robust silicon via structure and process'20138,298,917'Process for wet singulation using a dicing singulation structure'20128,295,056'Silicon carrier structure and method of forming same'20128,290,008'Silicon carrier optoelectronic packaging'20128,263,497'High-yield method of exposing and contacting through-silicon vias'20128,247,271'Formation of alpha particle shields in chip packaging'20128,242,591'Electrostatic chucking of an insulator handle substrate'20128,227,264'Reworkable electronic device assembly and method'20128,198,734'Silicon-on-insulator structures for through via in silicon carriers'20128,187,923'Laser release process for very thin Si-carrier build'20128,173,541'Chip carrier substrate including capacitor and method for fabrication thereof'20128,138,036'Through silicon via and method of fabricating same'20128,115,302'Electronic module with carrier substrates, multiple integrated circuit (IC) chips and microchannel cooling device'20128,080,876'Structure and method for creating reliable deep via connections in a silicon carrier'20118,012,796'Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers'20117,990,711'Double-face heat removal of vertically integrated chip-stacks utilizing combined symmetric silicon carrier fluid cavity and micro-channel cold plate'20117,948,077'Integrated circuit chip module with microchannel cooling device having specific fluid channel arrangement'20117,936,060'Reworkable electronic device assembly and method'20117,902,069'Small area, robust silicon via structure and process'20117,888,786'Electronic module comprising memory and integrated circuit processor chips formed on a microchannel cooling device'20117,820,521'Conductive through via structure and process for electronic device carriers'20107,741,722'Through-wafer vias'20107,741,226'Optimal tungsten through wafer via and process of fabricating same'20107,719,079'Chip carrier substrate capacitor and method for fabrication thereof'20107,678,696'Method of making through wafer vias'20107,645,701'Silicon-on-insulator structures for through via in silicon carriers'20107,615,405'Method for precision assembly of integrated circuit chip packages'20097,514,290'Chip-to-wafer integration technology for three-dimensional chip stacking'20097,501,708'Microelectronic device connection structure'20097,488,680'Conductive through via process for electronic device carriers'20097,449,067'Method and apparatus for filling vias'20087,316,831'Tilted vertical alignment of liquid crystals employing inorganic thin film composition and ion beam treatment'20087,282,391'Method for precision assembly of integrated circuit chip packages'20077,276,787'Silicon chip carrier with conductive through-vias and method for fabricating same'20077,230,334'Semiconductor integrated circuit chip packages having integrated microchannel cooling modules'20077,019,402'Silicon chip carrier with through-vias using laser assisted chemical vapor deposition of conductor'20066,872,974'Low threshold voltage instability amorphous silicon field effect transistor structure and biasing for active matrix organic light-emitting diodes'20056,767,828'Method for forming patterns for semiconductor devices'20046,731,064'Yield enchancement pixel structure for active matrix organic light-emitting diode displays'20046,731,361'High resolution in-plane switching mode TFT-LCD'20046,724,449'Vertical aligned liquid crystal display and method using dry deposited alignment layer films'20046,682,786'Liquid crystal display cell having liquid crystal molecules in vertical or substantially vertical alignment'20046,660,341'Tilted vertical alignment of liquid crystals employing inorganic thin film composition and ion beam treatment'20036,620,719'Method of forming ohmic contacts using a self doping layer for thin-film transistors'20036,580,127'High performance thin film transistor and active matrix process for flat panel displays'20036,566,687'Metal induced self-aligned crystallization of Si layer for TFT'20036,403,407'Method of forming fully self-aligned TFT with improved process window'20026,338,988'Method for fabricating self-aligned thin-film transistors to define a drain and source in a single photolithographic step'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2021Patents assigned to IBM (112)· patent assignee history
2002–2008Based in Mohegan Lake, NY, US· patent location history
2007–2021Based in Yorktown Heights, NY, US· patent location history
2011–2015Patents assigned to ANDRY PAUL S (19)· patent assignee history
2011–2015Patents assigned to TSANG CORNELIA K (12)· patent assignee history
2012–2013Patents assigned to SPROGIS EDMUND J (7)· patent assignee history
2012–2015Patents assigned to ANDRY PAUL STEPHEN (6)· patent assignee history
2018Based in Westchester, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 112 | 2002–2021 |
| ANDRY PAUL Sself | 19 | 2011–2015 |
| TSANG CORNELIA K | 12 | 2011–2015 |
| SPROGIS EDMUND J | 7 | 2012–2013 |
| ANDRY PAUL STEPHENself | 6 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Yorktown Heights, New York, US | 98 | 2007–2021 |
| Mohegan Lake, New York, US | 16 | 2002–2008 |
| Westchester, New York, US | 1 | 2018 |