Inventor

Christophe Maleville

Inventor

La Terrasse, FR

Overview

53→

Patents

2002–2018

Patent span

Electricity

Primary field (CPC H)

Patents· 53 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1036%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1031%

H10DInorganic electric semiconductor devices8%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%

H01LSemiconductor devices5%

Y10TTechnical subjects covered by former us classification3%

C30BSingle-crystal growth2%

G01NInvestigating or analysing materials by determining their chemical or physical properties2%

H01JElectric discharge tubes or discharge lamps1%

H10HInorganic light-emitting semiconductor devices having potential barriers1%

PatentTitleYear

10,002,882Method for manufacturing a high-resistivity semiconductor-on-insulator substrate including an RF circuit overlapping a doped region in the substrate2018 9,824,915'Structure for radiofrequency applications and process for manufacturing such a structure'2017 9,818,874'Method for fabricating semiconductor structures including fin structures with different strain states, and related semiconductor structures'2017 9,576,798'Method for fabricating semiconductor layers including transistor channels having different strain states, and related semiconductor layers'2017 9,349,865'Method for fabricating semiconductor structures including fin structures with different strain states, and related semiconductor structures'2016 9,219,150'Method for fabricating semiconductor structures including fin structures with different strain states, and related semiconductor structures'2015 9,209,301'Method for fabricating semiconductor layers including transistor channels having different strain states, and related semiconductor layers'2015 8,609,514'Process for the transfer of a thin film comprising an inclusion creation step'2013 8,470,712'Process for the transfer of a thin film comprising an inclusion creation step'2013 8,216,917'Method for fabricating a semiconductor on insulator type substrate'2012 8,058,149'Method for fabricating a semiconductor substrate'2011 7,972,939'Transfer method with a treatment of a surface to be bonded'2011 7,956,441'Method of increasing the area of a useful layer of material transferred onto a support'2011 7,919,391'Methods for preparing a bonding surface of a semiconductor wafer'2011 7,883,994'Process for the transfer of a thin film'2011 7,812,942'Method for detecting surface defects on a substrate and device using said method'2010 7,749,908'Edge removal of silicon-on-insulator transfer wafer'2010 7,749,910'Method of reducing the surface roughness of a semiconductor wafer'2010 7,749,862'Methods for minimizing defects when transferring a semiconductor useful layer'2010 7,645,392'Methods for preparing a bonding surface of a semiconductor wafer'2010 7,615,464'Transfer method with a treatment of a surface to be bonded'2009 7,585,793'Method for applying a high temperature heat treatment to a semiconductor wafer'2009 7,544,058'Method for high-temperature annealing a multilayer wafer'2009 7,465,645'Method of detaching a layer from a wafer using a localized starting area'2008 7,452,584'Method of increasing the area of a useful layer of material transferred onto a support'2008 7,413,964'Method of revealing crystalline defects in a bulk substrate'2008 7,300,856'Process for detaching layers of material'2007 7,297,611'Method for producing thin layers of semiconductor material from a donor wafer'2007 7,294,557'Method of increasing the area of a useful layer of material transferred onto a support'2007 7,285,471'Process for transfer of a thin layer formed in a substrate with vacancy clusters'2007 7,235,461'Method for bonding semiconductor structures together'2007 7,229,899'Process for the transfer of a thin film'2007 7,190,029'Preventive treatment method for a multilayer semiconductor wafer'2007 7,138,325'Method of manufacturing a wafer'2006 7,138,344'Method for minimizing slip line faults on a semiconductor wafer surface'2006 7,081,399'Method for producing a high quality useful layer on a substrate utilizing helium and hydrogen implantations'2006 7,071,077'Method for preparing a bonding surface of a semiconductor layer of a wafer'2006 7,048,867'Method of increasing the area of a useful layer of material transferred onto a support'2006 7,049,250'Heat treatment for edges of multilayer semiconductor wafers'2006 7,022,586'Method for recycling a substrate'2006 6,987,051'Method of making cavities in a semiconductor wafer'2006 6,941,795'Method for evaluating particle concentrations in a clean room or machine mini-environment'2005 6,939,783'Preventive treatment method for a multilayer semiconductor wafer'2005 6,903,032'Method for preparing a semiconductor wafer surface'2005 6,884,697'Process for cleaving a wafer layer from a donor wafer'2005 6,853,802'Heat treatment for edges of multilayer semiconductor wafers'2005 6,833,314'Method of characterizing implantation of a species in a substrate by surface imaging'2004 6,828,216'Process for detaching layers of material'2004 6,756,286'Method for transferring a thin film comprising a step of generating inclusions'2004 6,720,640'Method for reclaiming delaminated wafer and reclaimed delaminated wafer'2004 6,596,610'Method for reclaiming delaminated wafer and reclaimed delaminated wafer'2003 6,429,094'Treatment process for molecular bonding and unbonding of two structures'2002 6,403,450'Heat treatment method for semiconductor substrates'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2013Patents assigned to COMMISSARIAT ENERGIE ATOMIQUE (9)· patent assignee history

2002–2013Based in La Terrasse, FR· patent location history

2002–2010Based in Bernin, FR· patent location history

2003–2018Patents assigned to SOITEC SILICON ON INSULATOR (44)· patent assignee history

2003–2004Patents assigned to SHINETSU HANDOTAI KK (2)· patent assignee history

2005–2006Based in La Terasse, FR· patent location history

2010Patents assigned to ALTATECH SEMICONDUCTOR (1)· patent assignee history

2011–2013Patents assigned to MALEVILLE CHRISTOPHE (3)· patent assignee history

2015–2018Based in Laterasse, FR· patent location history

2017Based in Lumbin, FR· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
SOITEC SILICON ON INSULATOR	44	2003–2018
COMMISSARIAT ENERGIE ATOMIQUE	9	2002–2013
MALEVILLE CHRISTOPHEself	3	2011–2013
SHINETSU HANDOTAI KK	2	2003–2004
ALTATECH SEMICONDUCTOR	1	2010

Locations

Location	Patents	Span
La Terrasse, FR	38	2002–2013
Laterasse, FR	6	2015–2018
Bernin, FR	4	2002–2010
La Terasse, FR	3	2005–2006
Lumbin, FR	1	2017