Inventor

Jeffrey Junhao Xu

Inventor

San Diego, CA, US

Overview

65→

Patents

2010–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 65 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices29%

H10DInorganic electric semiconductor devices24%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%

G06FElectric digital data processing2%

G11CStatic stores2%

H10BElectronic memory devices2%

B82YSpecific uses or applications of nanostructures1%

B33YAdditive manufacturing, i.e. manufacturing of three-dimensional [3d] objects by additive deposition, additive agglomeration or additive layering, e.g. by 3d printing, stereolithography or selective laser sintering1%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%

PatentTitleYear

11,054,119Lamp for mounting in an opening through a planar substrate, and an installation method2021 10,559,501Self-aligned quadruple patterning process for Fin pitch below 20nm2020 10,510,872FinFETs and methods for forming the same2019 10,504,840Reducing tip-to-tip distance between end portions of metal lines formed in an interconnect layer of an integrated circuit (IC)2019 10,497,702Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent MOS standard cells2019 10,497,625Method and apparatus of multi threshold voltage CMOS2019 10,439,039Integrated circuits including a FinFET and a nanostructure FET2019 10,374,063FinFETs and methods for forming the same2019 10,354,912Forming self-aligned vertical interconnect accesses (VIAs) in interconnect structures for integrated circuits (ICs)2019 10,347,579Reducing tip-to-tip distance between end portions of metal lines formed in an interconnect layer of an integrated circuit (IC)2019 10,283,526Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop2019 10,163,792Semiconductor device having an airgap defined at least partially by a protective structure2018 10,157,992Nanowire device with reduced parasitics2018 10,141,305Semiconductor devices employing field effect transistors (FETs) with multiple channel structures without shallow trench isolation (STI) void-induced electrical shorts2018 10,115,723Complementary metal oxide semiconductor (CMOS) devices employing plasma-doped source/drain structures and related methods2018 10,102,898Ferroelectric-modulated Schottky non-volatile memory2018 10,090,244Standard cell circuits employing high aspect ratio voltage rails for reduced resistance2018 10,079,293Semiconductor device having a gap defined therein2018 10,062,763Method and apparatus for selectively forming nitride caps on metal gate2018 10,043,796Vertically stacked nanowire field effect transistors2018 10,032,678Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices2018 9,985,014Minimum track standard cell circuits for reduced area2018 9,953,979Contact wrap around structure2018 9,941,156Systems and methods to reduce parasitic capacitance2018 9,922,880'Method and apparatus of multi threshold voltage CMOS'2018 9,876,123Non-volatile one-time programmable memory device2018 9,871,121'Semiconductor device having a gap defined therein'2018 9,824,936'Adjacent device isolation'2017 9,806,177'FinFETs and methods for forming the same'2017 9,799,560'Self-aligned structure'2017 9,793,164'Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices'2017 9,721,891'Integrated circuit devices and methods'2017 9,653,399'Middle-of-line integration methods and semiconductor devices'2017 9,620,454'Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods'2017 9,620,612'Intergrated circuit devices including an interfacial dipole layer'2017 9,576,801'High dielectric constant/metal gate (HK/MG) compatible floating gate (FG)/ferroelectric dipole non-volatile memory'2017 9,564,518'Method and apparatus for source-drain junction formation in a FinFET with in-situ doping'2017 9,543,248'Integrated circuit devices and methods'2017 9,536,973'Metal-oxide-semiconductor field-effect transistor with metal-insulator-semiconductor contact structure to reduce schottky barrier'2017 9,508,589'Conductive layer routing'2016 9,508,439'Non-volatile multiple time programmable memory device'2016 9,502,414'Adjacent device isolation'2016 9,502,283'Electron-beam (E-beam) based semiconductor device features'2016 9,496,181'Sub-fin device isolation'2016 9,478,541'Half node scaling for vertical structures'2016 9,478,490'Capacitor from second level middle-of-line layer in combination with decoupling capacitors'2016 9,478,637'Scaling EOT by eliminating interfacial layers from high-K/metal gates of MOS devices'2016 9,472,453'Systems and methods of forming a reduced capacitance device'2016 9,425,096'Air gap between tungsten metal lines for interconnects with reduced RC delay'2016 9,343,357'Selective conductive barrier layer formation'2016 9,306,066'Method and apparatus of stressed FIN NMOS FinFET'2016 9,299,840'FinFETs and methods for forming the same'2016 9,257,556'Silicon germanium FinFET formation by Ge condensation'2016 9,240,480'Metal-oxide-semiconductor field-effect transistor with metal-insulator semiconductor contact structure to reduce Schottky barrier'2016 9,219,152'Semiconductor device with a buried stressor'2015 9,196,583'Via material selection and processing'2015 9,165,929'Complementarily strained FinFET structure'2015 8,927,377'Methods for forming FinFETs with self-aligned source/drain'2015 8,853,025'FinFET/tri-gate channel doping for multiple threshold voltage tuning'2014 8,809,171'Methods for forming FinFETs having multiple threshold voltages'2014 8,703,565'Bottom-notched SiGe FinFET formation using condensation'2014 8,395,195'Bottom-notched SiGe FinFET formation using condensation'2013 8,338,259'Semiconductor device with a buried stressor'2012 7,892,929'Shallow trench isolation corner rounding'2011 7,737,554'Pitch by splitting bottom metallization layer'2010

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2010–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (11)· patent assignee history

2010–2019Based in Jhubei City, TW· patent location history

2012–2016Patents assigned to XU JEFFREY JUNHAO (3)· patent assignee history

2012–2013Patents assigned to CHANG CHIH-HAO (2)· patent assignee history

2015–2020Patents assigned to QUALCOMM INC (48)· patent assignee history

2015–2020Based in San Diego, CA, US· patent location history

2016–2019Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (5)· patent assignee history

2021Based in Eindhoven, NL· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
QUALCOMM INC	48	2015–2020
TAIWAN SEMICONDUCTOR MFG	11	2010–2016
TAIWAN SEMICONDUCTOR MFG CO LTD	5	2016–2019
XU JEFFREY JUNHAOself	3	2012–2016
CHANG CHIH-HAO	2	2012–2013

Locations

Location	Patents	Span
San Diego, California, US	48	2015–2020
Jhubei City, TW	16	2010–2019
Eindhoven, NL	1	2021