Inventor
Lance E. Hacking
Inventor
Austin, TX, US
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing68%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use22%
G01RMeasuring electric variables5%
G11CStatic stores3%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%
PatentTitleYear
9,830,954Method and system for dynamic power management of memories20179,372,768'Debug interface'20169,189,439'Interface logic for a multi-core system-on-a-chip (SoC)'20159,189,302'Technique for monitoring activity within an integrated circuit'20158,656,411'Technique for monitoring activity within an integrated circuit'20148,650,629'Interface logic for a multi-core system-on-a-chip (SoC)'20148,412,855'Write combining protocol between processors and chipsets'20138,392,728'Reducing idle leakage power in an IC'20138,312,309'Technique for promoting determinism among multiple clock domains'20128,289,850'Interconnect bandwidth throttler'20128,050,177'Interconnect bandwidth throttler'20117,877,619'Power mode control method and circuitry'20117,707,350'Bus interconnect switching mechanism'20107,676,603'Write combining protocol between processors and chipsets'20107,360,103'P-state feedback to operating system with hardware coordination'20087,315,952'Power state coordination between devices sharing power-managed resources'20087,284,118'Method and apparatus for synchronizing load operations'20077,272,741'Hardware coordination of power management activities'20077,249,245'Globally observing load operations prior to fence instruction and post-serialization modes'20076,978,357'Method and apparatus for performing cache segment flush and cache segment invalidation operations'20056,862,679'Synchronization of load operations using load fence instruction in pre-serialization/post-serialization mode'20056,289,431'Method and apparatus for accessing more than 4 Gigabytes of physical memory with 4-byte table entries'20016,073,210'Synchronization of weakly ordered write combining operations using a fencing mechanism'20006,014,735'Instruction set extension using prefixes'20005,946,713'Memory attribute palette'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2017Patents assigned to INTEL CORP (24)· patent assignee history
1999–2007Based in Portland, OR, US· patent location history
2001Based in Hillsboro, OR, US· patent location history
2007–2017Based in Austin, TX, US· patent location history
2011–2017Patents assigned to HACKING LANCE E (5)· patent assignee history
2011–2013Patents assigned to PATEL RAJESH (3)· patent assignee history
2011–2014Patents assigned to RACHAKONDA RAMANA (3)· patent assignee history
2012–2013Patents assigned to HACKING LANCE (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 24 | 1999–2017 |
| HACKING LANCE Eself | 5 | 2011–2017 |
| HACKING LANCEself | 3 | 2012–2013 |
| PATEL RAJESH | 3 | 2011–2013 |
| RACHAKONDA RAMANA | 3 | 2011–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 17 | 2007–2017 |
| Portland, OR, US | 7 | 1999–2007 |
| Hillsboro, OR, US | 1 | 2001 |