Inventor
Brian E. Curcio
Inventor
San Diego, CA, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H05Kprimary
H05KPrinted circuits26%
Y10TTechnical subjects covered by former us classification26%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests11%
B41JTypewriters7%
B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form5%
C09DCoating compositions, e.g. paints, varnishes or lacquers4%
B23KSoldering or unsoldering2%
G03GElectrography2%
H01BCables2%
PatentTitleYear
9,798,259'Electrostatic ink compositions, methods and print substrates'20178,596,746'Inkjet pen/printhead with shipping fluid'20138,474,934'Method for improving gloss of a print'20138,356,878'Method of printing images'20138,267,498'Methods, apparatus and articles of manufacture to control gloss quality'20127,914,110'Purging fluid from fluid-ejection nozzles by performing spit-wipe operations'20117,402,254'Method and structure for producing Z-axis interconnection assembly of printed wiring board elements'20087,303,639'Method for producing Z-axis interconnection assembly of printed wiring board elements'20077,076,869'Solid via layer to layer interconnect'20066,969,436'Method and structure for producing Z-axis interconnection assembly of printed wiring board elements'20056,955,849'Method and structure for small pitch z-axis electrical interconnections'20056,790,305'Method and structure for small pitch z-axis electrical interconnections'20046,776,852'Process of removing holefill residue from a metallic surface of an electronic substrate'20046,645,607'Method and structure for producing Z-axis interconnection assembly of printed wiring board elements'20036,638,607'Method and structure for producing Z-axis interconnection assembly of printed wiring board elements'20036,634,543'Method of forming metallic z-interconnects for laminate chip packages and boards'20036,581,280'Method for filling high aspect ratio via holes in electronic substrates'20036,570,102'Structure for high speed printed wiring boards with multiple differential impedance-controlled layer'20036,504,111'Solid via layer to layer interconnect'20036,465,084'Method and structure for producing Z-axis interconnection assembly of printed wiring board elements'20026,452,117'Method for filling high aspect ratio via holes in electronic substrates and the resulting holes'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2008Patents assigned to IBM (15)· patent assignee history
2002–2008Based in Binghamton, NY, US· patent location history
2003–2017Based in San Diego, CA, US· patent location history
2011–2013Patents assigned to HEWLETT PACKARD DEVELOPMENT CO (5)· patent assignee history
2012–2013Patents assigned to CURCIO BRIAN E (4)· patent assignee history
2012–2013Patents assigned to BLAIR DUSTIN W (2)· patent assignee history
2012–2013Patents assigned to HADDICK GLENN THOMAS (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 15 | 2002–2008 |
| HEWLETT PACKARD DEVELOPMENT CO | 5 | 2011–2013 |
| CURCIO BRIAN Eself | 4 | 2012–2013 |
| BLAIR DUSTIN W | 2 | 2012–2013 |
| HADDICK GLENN THOMAS | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Diego, California, US | 11 | 2003–2017 |
| Binghamton, New York, US | 10 | 2002–2008 |