Inventor
Vinod Kariat
Inventor
Sunnyvale, CA, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing95%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
PatentTitleYear
9,129,078'Static timing analysis of integrated circuit designs with flexible noise and delay models of circuit stages'20158,966,421'Static timing analysis methods for integrated circuit designs using a multi-CCC current source model'20158,694,934'Method and apparatus for multi-die thermal analysis'20148,631,369'Methods, systems, and apparatus for timing and signal integrity analysis of integrated circuits with semiconductor process variations'20148,595,669'Flexible noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs'20138,566,760'Method and apparatus for multi-die thermal analysis'20138,543,954'Concurrent noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs'20138,543,952'Method and apparatus for thermal analysis of through-silicon via (TSV)'20138,533,644'Multi-CCC current source models and static timing analysis methods for integrated circuit designs'20138,516,420'Sensitivity and static timing analysis for integrated circuit designs using a multi-CCC current source model'20138,504,958'Method and apparatus for thermal analysis'20138,201,113'Method and apparatus for multi-die thermal analysis'20128,104,007'Method and apparatus for thermal analysis'20128,103,996'Method and apparatus for thermal analysis of through-silicon via (TSV)'20128,104,006'Method and apparatus for thermal analysis'20127,900,166'Method to produce an electrical model of an integrated circuit substrate and related system and article of manufacture'20117,882,471'Timing and signal integrity analysis of integrated circuits with semiconductor process variations'20117,877,713'Method and apparatus for substrate noise analysis using substrate tile model and tile grid'20116,836,873'Static noise analysis with noise window estimation and propagation'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2015Patents assigned to CADENCE DESIGN SYSTEMS INC (19)· patent assignee history
2004–2015Based in Sunnyvale, CA, US· patent location history
2012–2014Patents assigned to KARIAT VINOD (13)· patent assignee history
2012–2014Patents assigned to PRAMONO EDDY (8)· patent assignee history
2012–2014Patents assigned to ZHAN YONG (7)· patent assignee history
2012–2014Patents assigned to KELLER IGOR (6)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CADENCE DESIGN SYSTEMS INC | 19 | 2004–2015 |
| KARIAT VINODself | 13 | 2012–2014 |
| PRAMONO EDDY | 8 | 2012–2014 |
| ZHAN YONG | 7 | 2012–2014 |
| KELLER IGOR | 6 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Sunnyvale, California, US | 19 | 2004–2015 |