Inventor
Jackson Chung Peng Kong
Inventor
Tanjung Tokong, MY
Overview
Patents· 43 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1024%
H01LSemiconductor devices24%
H05KPrinted circuits14%
G06FElectric digital data processing8%
H01PWaveguides3%
H10DInorganic electric semiconductor devices3%
H01FMagnets3%
H01GCapacitors3%
H01RElectrically-conductive connections3%
H03HImpedance networks, e.g. resonant circuits2%
PatentTitleYear
11,121,074Packaged die stacks with stacked capacitors and methods of assembling same202111,049,801Encapsulated vertical interconnects for high-speed applications and methods of assembling same202111,037,874Plane-less voltage reference interconnects202110,856,407Transmission line design with routing-over-void compensation202010,840,177Interposer with flexible portion202010,734,333Semiconductor package having inductive lateral interconnects202010,734,318Folded semiconductor package architectures and methods of assembling same202010,716,209Fiber weave-sandwiched differential pair routing technique202010,652,999Mutual inductance suppressor for crosstalk immunity enhancement202010,651,127Ring-in-ring configurable-capacitance stiffeners and methods of assembling same202010,643,983Extended stiffener for platform miniaturization202010,633,898Micro-hinge for an electronic device202010,606,316Flexible computing device that includes a plurality of displays202010,593,618Packaged die stacks with stacked capacitors and methods of assembling same202010,580,761Systems in packages including wide-band phased-array antennas and methods of assembling same202010,541,200Over-molded IC packages with embedded voltage reference plane and heater spreader202010,504,854Through-stiffener inerconnects for package-on-package apparatus and methods of assembling same201910,503,211Multi-orientation display device201910,484,231Routing-over-void-T-line-compensation201910,403,604Stacked package assembly with voltage reference plane201910,396,047Semiconductor package with package components disposed on a package substrate within a footprint of a die201910,396,038Flexible packaging architecture201910,354,957Electrical interconnect for a flexible electronic package201910,317,938Apparatus utilizing computer on package construction201910,319,698Microelectronic device package having alternately stacked die201910,158,339Capacitive compensation structures using partially meshed ground planes201810,153,253Package-bottom through-mold via interposers for land-side configured devices for system-in-package apparatus201810,108,227Techniques for providing an interface component for a wearable device201810,085,342Microelectronic device having an air core inductor201810,083,922Inductor interconnect201810,079,158Vertical trench routing in a substrate201810,014,710Foldable fabric-based packaging solution20189,893,444'Board-edge interconnection module with integrated capacitive coupling for enabling ultra-mobile computing devices'20189,812,425'Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same'20179,646,953'Integrated circuit packaging techniques and configurations for small form-factor or wearable devices'20179,606,949'Universal scalable system: on-the-fly system performance conversion via PC-on-a-card and USB for smart devices and IoT enabling'20179,596,749'Circuit board having a signal layer with signal traces and a reference plane with an additional signal trace larger than the signal traces'20179,552,995'Electrical interconnect for an electronic package'2017D0773452'Electronic device with flexible hinge'20169,478,524'Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same'20169,360,896'Low-profile hinge for an electronic device'2016D0756349'Portable computing device with low profile hinge'20169,136,251'Method to enable controlled side chip interconnection for 3D integrated packaging system'2015Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2015–2021Patents assigned to INTEL CORP (43)· patent assignee history
2015Patents assigned to CHEAH BOK ENG (1)· patent assignee history
2015Patents assigned to KONG JACKSON CHUNG PENG (1)· patent assignee history
2015Patents assigned to OOI KOOI CHI (1)· patent assignee history
2015Patents assigned to PERIAMAN SHANGGAR (1)· patent assignee history
2015–2017Based in Bayan Lepas, MY· patent location history
2016–2021Based in Tanjung Tokong, MY· patent location history
2019–2020Based in Penang, MY· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 43 | 2015–2021 |
| CHEAH BOK ENG | 1 | 2015 |
| KONG JACKSON CHUNG PENGself | 1 | 2015 |
| OOI KOOI CHI | 1 | 2015 |
| PERIAMAN SHANGGAR | 1 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tanjung Tokong, MY | 38 | 2016–2021 |
| Bayan Lepas, MY | 3 | 2015–2017 |
| Penang, MY | 2 | 2019–2020 |