Inventor
Otto A. Torreiter
Inventor
Leinfelden-Echterdingen, DE
Overview
Patents· 34 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G01Rprimary
G01RMeasuring electric variables37%
G11CStatic stores12%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
G06FElectric digital data processing8%
H01LSemiconductor devices8%
Y10TTechnical subjects covered by former us classification8%
H05KPrinted circuits5%
H04LTransmission of digital information, e.g. telegraphic communication2%
PatentTitleYear
10,288,684On-chip hardware-controlled window strobing201910,281,527On-chip hardware-controlled window strobing201910,114,069Method for electrical testing of a 3-D chip stack201810,114,914Layout effect characterization for integrated circuits201810,056,346Chip attach frame20189,977,053Wafer probe alignment20189,927,463'Wafer probe alignment'20189,904,748'Layout effect characterization for integrated circuits'20189,740,813'Layout effect characterization for integrated circuits'20179,709,625'Measuring power consumption in an integrated circuit'20179,686,895'Chip attach frame'20179,679,665'Method for performing built-in self-tests'20179,627,017'RAM at speed flexible timing and setup control'20179,627,090'RAM at speed flexible timing and setup control'20179,620,244'Determining categories for memory fail conditions'20179,496,188'Soldering three dimensional integrated circuits'20169,401,222'Determining categories for memory fail conditions'20169,322,848'Ball grid array configuration for reliable testing'20169,250,289'System for electrical testing and manufacturing of a 3-D chip stack and method'20169,217,758'Ball grid array configuration for reliable testing'20159,094,306'Network power fault detection'20158,866,504'Determining local voltage in an electronic system'20148,659,310'Method and system for performing self-tests in an electronic system'20148,535,956'Chip attach frame'20138,010,934'Method and system for testing bit failures in array elements of an electronic circuit'20117,921,388'Wordline booster design structure and method of operating a wordine booster circuit'20117,650,554'Method and an integrated circuit for performing a test'20107,636,254'Wordline booster circuit and method of operating a wordline booster circuit'20096,774,656'Self-test for leakage current of driver/receiver stages'20046,725,171'Self-test with split, asymmetric controlled driver output stage'20046,127,254'Method and device for precise alignment of semiconductor chips on a substrate'20005,742,616'System and method testing computer memories'19985,485,473'Method and system for testing an integrated circuit featuring scan design'19965,369,358'Method of ensuring electrical contact between test probes and chip pads through the use of vibration and nondestructive deformation'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–2019Patents assigned to IBM (32)· patent assignee history
1994–2019Based in Leinfelden-Echterdingen, DE· patent location history
2013–2017Patents assigned to ECKERT MARTIN (4)· patent assignee history
2014–2017Patents assigned to FRECH ROLAND (3)· patent assignee history
2014–2017Patents assigned to SUPPER JOCHEN (2)· patent assignee history
2014–2018Based in Boeblingen, DE· patent location history
2015–2016Patents assigned to GLOBALFOUNDRIES INC (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 32 | 1994–2019 |
| ECKERT MARTIN | 4 | 2013–2017 |
| FRECH ROLAND | 3 | 2014–2017 |
| GLOBALFOUNDRIES INC | 2 | 2015–2016 |
| SUPPER JOCHEN | 2 | 2014–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Leinfelden-Echterdingen, DE | 28 | 1994–2019 |
| Boeblingen, DE | 6 | 2014–2018 |