Inventor
Brian Schorr
Inventor
Beaverton, OR, US
Overview
Patents· 4 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices33%
H10DInorganic electric semiconductor devices33%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1033%
PatentTitleYear
10,686,038Reverse conducting IGBT incorporating epitaxial layer field stop zone202010,170,559Reverse conducting IGBT incorporating epitaxial layer field stop zone and fabrication method20197,015,116'Stress-relieved shallow trench isolation (STI) structure and method for forming the same'20066,791,155'Stress-relieved shallow trench isolation (STI) structure and method for forming the same'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2006Patents assigned to INTEGRATED DEVICE TECH (2)· patent assignee history
2004–2006Based in Portland, OR, US· patent location history
2019–2020Patents assigned to ALPHA & OMEGA SEMICONDUCTOR CAYMAN LTD (2)· patent assignee history
2019–2020Based in Beaverton, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ALPHA & OMEGA SEMICONDUCTOR CAYMAN LTD | 2 | 2019–2020 |
| INTEGRATED DEVICE TECH | 2 | 2004–2006 |
Locations
| Location | Patents | Span |
|---|---|---|
| Beaverton, OR, US | 2 | 2019–2020 |
| Portland, OR, US | 2 | 2004–2006 |