Inventor
Hiromitsu Hada
Inventor
Tokyo, JP
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices18%
H10NElectric solid-state devices not otherwise provided for18%
H01LSemiconductor devices15%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
H10DInorganic electric semiconductor devices8%
G11CStatic stores7%
G01RMeasuring electric variables3%
H01CResistors3%
C23CCoating metallic material1%
PatentTitleYear
10,256,400Semiconductor device and method of manufacturing the same20199,754,998'Semiconductor device and operation method for same'20179,406,877'Semiconductor device and method of manufacturing the same'20169,245,789'Method for forming wiring'20169,231,207'Method for forming resistance changing element capable of operating at low voltage'20169,059,082'Semiconductor device and operation method for same'20159,059,028'Semiconductor device and method for manufacturing same'20159,059,402'Resistance-variable element and method for manufacturing the same'20159,029,825'Semiconductor device and manufacturing method for semiconductor device'20158,946,668'Semiconductor device and method of manufacturing the same'20158,946,672'Resistance changing element capable of operating at low voltage, semiconductor device, and method for forming resistance change element'20158,816,312'Semiconductor device'20148,796,659'Variable resistance element, semiconductor device including variable resistance element, and methods for manufacturing variable resistance element and semiconductor device'20148,536,629'Semiconductor device and method for manufacturing the same'20136,030,894'Method for manufacturing a semiconductor device having contact plug made of Si/SiGe/Si'20005,946,570'Process for fabricating semiconductor device having semiconductor layers epitaxially grown from active areas without short-circuit on field insulating layer'19995,930,675'Process of forming inter-level connection without increase of contact resistance'19995,909,059'Semiconductor device having contact plug and method for manufacturing the same'19995,895,948'Semiconductor device and fabrication process thereof'19995,861,653'Semiconductor device having gaseous isolating layer formed in inter-level insulating layer and process of fabrication thereof'19995,753,555'Method for forming semiconductor device'19985,663,651'Method of separately determining plug resistor and interfacial resistor and test pattern for the same'19975,640,097'Test pattern for separately determining plug resistance and interfactial resistance'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997–2019Patents assigned to NEC CORP (23)· patent assignee history
1997–2019Based in Tokyo, JP· patent location history
2013–2019Patents assigned to HADA HIROMITSU (11)· patent assignee history
2013–2019Patents assigned to TADA MUNEHIRO (10)· patent assignee history
2013–2015Based in Minato-ku, JP· patent location history
2014–2019Patents assigned to SAKAMOTO TOSHITSUGU (6)· patent assignee history
2014–2015Patents assigned to MIYAMURA MAKOTO (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NEC CORP | 23 | 1997–2019 |
| HADA HIROMITSUself | 11 | 2013–2019 |
| TADA MUNEHIRO | 10 | 2013–2019 |
| SAKAMOTO TOSHITSUGU | 6 | 2014–2019 |
| MIYAMURA MAKOTO | 3 | 2014–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 20 | 1997–2019 |
| Minato-ku, JP | 3 | 2013–2015 |