Inventor
Yi-Jing Lee
Inventor
Hsinchu, TW
Overview
Patents· 58 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices31%
H01LSemiconductor devices30%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
H10BElectronic memory devices4%
G08GTraffic control systems1%
H04WWireless communication networks1%
G01CMeasuring distances, levels or bearings1%
G01SRadio direction-finding1%
PatentTitleYear
10,847,638Increasing source/drain dopant concentration to reduced resistance202010,840,355Increasing source/drain dopant concentration to reduced resistance202010,804,163Method of metal gate formation and structures formed by the same202010,770,359Semiconductor device and method202010,754,003Method for determining the position of mobile node and related communication system, road side unit, and vehicle thereof202010,727,229Structure and method for semiconductor device202010,714,487Semiconductor device and manufacturing method of a semiconductor device202010,665,094Method, mobile device, and system for the message transmission of a vulnerable road user202010,665,674FinFET semiconductor device with germanium diffusion over silicon fins202010,622,261FinFET devices with unique shape and the fabrication thereof202010,546,784Semiconductor device having merged epitaxial features with arc-like bottom surface and method of making the same202010,516,037Method of forming shaped source/drain epitaxial layers of a semiconductor device201910,515,858Semiconductor device and method201910,510,868Fin Field-Effect Transistors and methods of forming the same201910,510,753Integrated circuit and manufacturing method thereof201910,504,993FinFET semiconductor device with germanium diffusion over silicon fins201910,490,552FinFET device having flat-top epitaxial features and method of making the same201910,355,105Fin field-effect transistors and methods of forming the same201910,170,375FinFET devices with unique fin shape and the fabrication thereof201910,170,483Semiconductor device, static random access memory cell and manufacturing method of semiconductor device201910,164,022FinFETs with strained well regions201810,164,023FinFETs with strained well regions201810,158,015FinFETs with strained well regions201810,115,826Semiconductor structure and the manufacturing method thereof201810,084,069Apparatus and method for FinFETs201810,049,936Semiconductor device having merged epitaxial features with Arc-like bottom surface and method of making the same20189,922,828'Apparatus and method for FinFETs'20189,922,975'Integrated circuit having field-effect trasistors with dielectric fin sidewall structures and manufacturing method thereof'20189,859,380'FinFETs with strained well regions'20189,825,036'Structure and method for semiconductor device'20179,780,174'Methods for forming semiconductor regions in trenches'20179,768,178'Semiconductor device, static random access memory cell and manufacturing method of semiconductor device'20179,748,142'FinFETs with strained well regions'20179,748,143'FinFETs with strained well regions'20179,722,051'Apparatus and method for FinFETs'20179,601,342'FinFETs with strained well regions'20179,559,099'Apparatus and method for FinFETs'20179,553,149'Semiconductor device with a strained region and method of making'20179,553,012'Semiconductor structure and the manufacturing method thereof'20179,548,303'FinFET devices with unique fin shape and the fabrication thereof'20179,530,776'FinFET semiconductor device with germanium diffusion over silicon fins'20169,484,265'Structure and method for semiconductor device'20169,455,320'FinFETs with strained well regions'20169,450,098'FinFET having superlattice stressor'20169,390,982'CMOS devices with reduced leakage and methods of forming the same'20169,385,234'FinFETs with strained well regions'20169,287,382'Structure and method for semiconductor device'20169,276,117'Structure and method and FinFET device'20169,269,777'Source/drain structures and methods of forming same'20169,224,734'CMOS devices with reduced leakage and methods of forming the same'20159,196,709'Methods for forming semiconductor regions in trenches'20159,159,824'FinFETs with strained well regions'20159,153,582'Apparatus and method for FinFETs'20159,123,633'Methods for forming semiconductor regions in trenches'20159,087,902'FinFETs with strained well regions'20158,994,002'FinFET having superlattice stressor'20158,815,712'Method for epitaxial re-growth of semiconductor region'20148,742,509'Apparatus and method for FinFETs'2014Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2014–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (14)· patent assignee history
2014–2015Patents assigned to KO CHIH-HSIN (3)· patent assignee history
2014–2015Patents assigned to LEE YI-JING (3)· patent assignee history
2014–2015Patents assigned to LIN YOU-RU (3)· patent assignee history
2014–2020Based in Hsinchu, TW· patent location history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (42)· patent assignee history
2020Based in New Taipei, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 42 | 2016–2020 |
| TAIWAN SEMICONDUCTOR MFG | 14 | 2014–2016 |
| KO CHIH-HSIN | 3 | 2014–2015 |
| LEE YI-JINGself | 3 | 2014–2015 |
| LIN YOU-RU | 3 | 2014–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 56 | 2014–2020 |
| New Taipei, TW | 2 | 2020 |