Inventor
Ramesh Gunna
Inventor
San Jose, CA, US
Overview
Patents· 38 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing69%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use22%
G11CStatic stores4%
G05FSystems for regulating electric or magnetic variables2%
H03KPulse technique2%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%
PatentTitleYear
10,901,484Fetch predition circuit for reducing power consumption in a processor202110,416,692Method and apparatus for reducing capacitor-induced noise201910,410,688Managing power state in one power domain based on power states in another power domain201910,401,938Single power plane dynamic voltage margin recovery for multiple clock domains201910,241,557Reducing power consumption in a processor201910,147,464Managing power state in one power domain based on power states in another power domain20189,626,185'IT instruction pre-decode'20179,405,544'Next fetch predictor return address stack'20169,367,471'Fetch width predictor'20169,354,886'Maintaining the integrity of an execution return address stack'20169,280,352'Lookahead scanning and cracking of microcode instructions in a dispatch queue'20168,959,320'Preventing update training of first predictor with mismatching second predictor for branch instructions with alternating pattern hysteresis'20158,892,841'Store handling in a processor'20148,566,528'Combining write buffer with dynamically adjustable flush metrics'20138,555,040'Indirect branch target predictor that prevents speculation if mispredict is expected'20138,364,907'Converting victim writeback to a fill'20138,359,414'Retry mechanism'20138,352,685'Combining write buffer with dynamically adjustable flush metrics'20138,347,040'Latency reduction for cache coherent bus-based cache'20138,341,379'R and C bit update handling'20128,301,843'Data cache block zero implementation'20128,255,670'Replay reduction for power saving'20128,239,638'Store handling in a processor'20128,171,326'L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power down'20128,131,946'Converting victim writeback to a fill'20127,991,928'Retry mechanism'20117,970,970'Non-blocking address switch with shallow per agent queues'20117,949,832'Latency reduction for cache coherent bus-based cache'20117,836,262'Converting victim writeback to a fill'20107,752,366'Non-blocking address switch with shallow per agent queues'20107,752,474'L1 cache flush when processor is entering low power mode'20107,739,476'R and C bit update handling'20107,707,361'Data cache block zero implementation'20107,702,858'Latency reduction for cache coherent bus-based cache'20107,647,518'Replay reduction for power saving'20107,529,866'Retry mechanism in cache coherent communication among agents'20097,461,190'Non-blocking address switch with shallow per agent queues'20087,398,361'Combined buffer for snoop, store merging, load miss, and writeback operations'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2021Based in San Jose, CA, US· patent location history
2010–2021Patents assigned to APPLE INC (35)· patent assignee history
2012–2014Patents assigned to GUNNA RAMESH (12)· patent assignee history
2012–2014Patents assigned to KADAMBI SUDARSHAN (5)· patent assignee history
2012–2016Patents assigned to BANNON PETER J (4)· patent assignee history
2013–2016Patents assigned to BEAUMONT-SMITH ANDREW J (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| APPLE INC | 35 | 2010–2021 |
| GUNNA RAMESHself | 12 | 2012–2014 |
| KADAMBI SUDARSHAN | 5 | 2012–2014 |
| BANNON PETER J | 4 | 2012–2016 |
| BEAUMONT-SMITH ANDREW J | 4 | 2013–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 38 | 2008–2021 |