Inventor

AMRITA MATHURIYA

Inventor

US

Overview

2021–2026

Patent span

Electricity

Primary field (CPC H)

Patents· 254 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices18%

H10BElectronic memory devices16%

G11CStatic stores15%

H01LSemiconductor devices11%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%

H03KPulse technique8%

G06FElectric digital data processing8%

G06NComputing arrangements based on specific computational models4%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%

H10NElectric solid-state devices not otherwise provided for3%

PatentTitleYear

12,593,456Method of fabricating transistors and stacked non-planar capacitors for memory and logic applications2026 12,562,204Non-linear polar material based multi-capacitor bit-cell with shared gain element with series transistor and individual access transistor2026 12,563,737Memory device fabrication through wafer bonding2026 12,554,462Asynchronous full-adder with majority or minority gates to generate an enable or an acknowledgement2026 12,525,543Integration process for fabricating embedded memory2026 12,524,204Ferroelectric or paraelectric based low power multiplier2026 12,524,205Asynchronous full-adder with majority or minority gates to generate sum true output2026 12,517,701Sequential reset mechanism for a chain of majority or minority gates having non-linear polar material2026 12,481,481Asynchronous carry-ripple adder with majority or minority gates2025 12,464,730Method of forming capacitors through wafer bonding2025 12,463,142Integrating embedded memory with logic interconnects2025 12,451,888Ripple carry adder with ferroelectric or paraelectric wide-input minority or majority gates2025 12,446,231Method of integrating a capacitor including a non-linear polar material with a transistor through wafer bonding2025 12,445,134Diode connected non-linear input capacitors based majority gate2025 12,436,739Non-linear polar material based low power multiplier with transmission-gate based reset mechanism2025 12,439,606Gate coupled non-linear polar material based capacitors for memory and logic2025 12,412,611Time decoupled write operations for non-linear polar material based memory2025 12,411,657Asynchronous full-adder with majority or minority gates to generate carry-out true output2025 12,414,306Method of fabricating memory devices using pocket integration2025 12,405,768Asynchronous full-adder with majority or minority gates to generate carry-out false output2025 12,379,898Asynchronous full-adder with majority or minority gates to generate sum false output2025 12,376,312Methods of fabricating planar capacitors on a shared plate electrode2025 12,374,377Ferroelectric or paraelectric wide-input minority or majority gate based low power adder2025 12,369,326Capacitor devices with shared electrode and methods of fabrication2025 12,349,365Drain coupled non-linear polar material based capacitors for memory and logic2025 12,347,476Apparatus and method to improve sensing noise margin in a non-linear polar material based bit-cell2025 12,334,127Non-linear polar material based multi-capacitor high density bit-cell2025 12,334,923Multi-cycle reset mechanism for a chain of majority gates having non-linear polar material2025 12,334,918Stacked non-planar capacitors based multi-function linear threshold gate with input based adaptive threshold2025 12,336,184Methods of fabricating trench capacitors on a shared plate electrode2025 12,328,878Integration of 2T-2025 12,322,743Multi-function threshold gate with input based adaptive threshold and with stacked non-planar paraelectric capacitors2025 12,324,163Planar capacitors with shared electrode and methods of fabrication2025 12,324,162Stacked capacitors with shared electrodes and methods of fabrication2025 12,316,319Multi-function linear threshold gate with input based adaptive threshold2025 12,308,064Random swap injection2025 12,308,836Method of adjusting threshold of a linear capacitive-input circuit2025 12,308,838Exclusive-or logic gate with non-linear input capacitors2025 12,308,837Multiplier with non-linear polar material2025 12,300,297Memory array with buried or backside word-line2025 12,294,370Area optimized ferroelectric or paraelectric based low power multiplier2025 12,289,104Ferroelectric or paraelectric based low power multiplier array2025 12,289,894Method of fabricating transistors and stacked planar capacitors for memory and logic applications2025 12,283,955Majority or minority based low power checkerboard carry save multiplier with inverted multiplier cells2025 12,283,571Ultra high-bandwidth artificial intelligence (AI) processor with DRAM under the processor2025 12,274,071Capacitor integrated with a transistor for logic and memory applications2025 12,272,675Method of forming 3D stacked compute and memory with copper pillars2025 12,265,494Multi-die mapping matrix multiplication2025 12,262,541Trench capacitors with shared electrode2025 12,262,543High density ferroelectric random access memory (FeRAM) devices and methods of fabrication2025 12,243,7973D stack of split graphics processing logic dies2025 12,238,935Embedded memory adjacent to non-memory2025 12,218,045Stacked planar capacitors based multi-function linear threshold gate with input based adaptive threshold2025 12,212,321Non-linear polar material based flip-flop2025 12,200,941Pillar capacitor and method of fabricating such2025 12,190,946Read disturb mitigation for non-linear polar material based multi-capacitor bit-cell2025 12,171,103Multi-input threshold gate having stacked and folded non-planar capacitors2024 12,166,011Method of forming an artificial intelligence processor with three-dimensional stacked memory2024 12,155,383Reset mechanism for an adder or a multiplier having paraelectric material2024 12,147,941Iterative monetization of precursor in process development of non-linear polar material and devices2024 12,147,747Area oriented logic synthesis2024 12,142,310Method of fabricating pedestal based memory devices using pocket integration2024 12,137,574Integration of ferroelectric memory devices having stacked electrodes with transistors2024 12,126,339Apparatus with selectable majority gate and combinational logic gate outputs2024 12,118,327Ripple carry adder with inverted ferroelectric or paraelectric based adders2024 12,118,330Low power multiplier with non-linear polar material based reset mechanism with sequential reset2024 12,113,097Ferroelectric capacitor integrated with logic2024 12,108,609Memory bit-cell with stacked and folded planar capacitors2024 12,107,579Method for conditioning majority or minority gate2024 12,108,607Devices with continuous electrode plate and methods of fabrication2024 12,108,608Memory devices with dual encapsulation layers and methods of fabrication2024 12,094,923Rapid thermal annealing (RTA) methodologies for integration of perovskite-material based memory devices2024 12,096,638One transistor and N memory element based memory bit-cell having stacked and folded planar memory elements with and without offset2024 12,094,511Write disturb mitigation for column multiplexed non-linear polar material based multi-capacitor bit-cell2024 12,086,410Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer2024 12,088,297Majority gate based low power ferroelectric based adder with reset mechanism2024 12,087,730Multi-input threshold gate having stacked and folded planar capacitors with and without offset2024 12,079,475Ferroelectric memory chiplet in a multi-dimensional packaging2024 12,069,866Pocket integration process for embedded memory2024 12,062,584Iterative method of multilayer stack development for device applications2024 12,041,7851TnC memory bit-cell having stacked and folded non-planar capacitors2024 12,034,086Trench capacitors with continuous dielectric layer and methods of fabrication2024 12,029,043Planar and trench capacitors with hydrogen barrier dielectric for logic and memory applications and methods of fabrication2024 12,026,034Method and apparatus for heuristic-based power gating of non-CMOS logic and CMOS based logic2024 12,022,662Planar and trench capacitors for logic and memory applications and methods of fabrication2024 12,019,492Method and apparatus for managing power in a multi-dimensional packaging2024 12,015,402Asynchronous consensus circuit with stacked ferroelectric non-planar capacitors2024 12,016,185Planar and trench capacitors for logic and memory applications2024 12,010,854Multi-level hydrogen barrier layers for memory applications and methods of fabrication2024 12,009,820Asynchronous consensus circuit with majority gate based on non-linear capacitors2024 12,001,266Method and apparatus for managing power of ferroelectric or paraelectric logic and CMOS based logic2024 11,997,8531TnC memory bit-cell having stacked and folded planar capacitors with lateral offset2024 11,996,438Pocket flow for trench capacitors integrated with planar capacitors on a same substrate and method of fabrication2024 11,985,832Planar and trench capacitors with hydrogen barrier dielectric for logic and memory applications2024 11,985,831Multi-function threshold gate with input based adaptive threshold and with stacked non-planar ferroelectric capacitors2024 11,978,762Planar capacitors with non-linear polar material staggered on a shared electrode2024 11,979,148Asynchronous consensus circuit with stacked linear or paraelectric planar capacitors2024 11,967,954Majority or minority logic gate with non-linear input capacitors without reset2024 11,961,877Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures2024 11,955,512Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures and methods of fabrication2024 11,955,153Multi-element gain memory bit-cell having stacked and folded planar memory elements with and without offset2024 11,942,133Pedestal-based pocket integration process for embedded memory2024 11,922,105Computer-aided design tool for minimum gate count initialization2024 11,909,391Asynchronous completion tree circuit using multi-function threshold gate with input based adaptive threshold2024 11,910,618Multi-element ferroelectric gain memory bit-cell having stacked and folded non-planar capacitors2024 11,908,704Method of fabricating a perovskite-material based planar capacitor using rapid thermal annealing (RTA) methodologies2024 11,901,891Asynchronous consensus circuit with stacked ferroelectric planar capacitors2024 11,903,219Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors2024 11,899,613Method and apparatus to process an instruction for a distributed logic having tightly coupled accelerator core and processor core in a multi-dimensional packaging2024 11,894,417Method of fabricating a perovskite-material based trench capacitor using rapid thermal annealing (RTA) methodologies2024 11,888,479Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism2024 11,875,836Apparatus and method for endurance of non-volatile memory banks via wear leveling with linear indexing2024 11,869,928Dual hydrogen barrier layer for memory devices2024 11,871,583Ferroelectric memory devices2024 11,869,562Apparatus and method for endurance of non-volatile memory banks via wear leveling in a round robin fashion2024 11,871,584Multi-level hydrogen barrier layers for memory applications2024 11,869,843Integrated trench and via electrode for memory device applications and methods of fabrication2024 11,863,184Asynchronous validity tree circuit using multi-function threshold gate with input based adaptive threshold2024 11,861,278Computer-aided design tool for gate pruning2024 11,861,279Computer-aided design tool for inverter minimization2024 11,863,183Low power non-linear polar material based threshold logic gate multiplier2024 11,862,517Integrated trench and via electrode for memory device applications2024 11,855,626Asynchronous consensus circuit with stacked linear or paraelectric non-planar capacitors2023 11,853,666Computer-aided design tool for wide-input logic initialization2023 11,855,627Asynchronous consensus circuit using multi-function threshold gate with input based adaptive threshold2023 11,854,593Ferroelectric memory device integrated with a transition electrode2023 11,841,757Method and apparatus for cycle-by-cycle clock gating of ferroelectric or paraelectric logic and CMOS based logic2023 11,844,223Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging2023 11,844,203Conductive and insulative hydrogen barrier layer for memory devices2023 11,844,225Dual hydrogen barrier layer for memory devices integrated with low density film for logic structures and methods of fabrication2023 11,837,268Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors with lateral offset2023 11,836,102Low latency and high bandwidth artificial intelligence processor2023 11,839,088Integrated via and bridge electrodes for memory array applications and methods of fabrication2023 11,839,070High density dual encapsulation materials for capacitors and methods of fabrication2023 11,832,451High density ferroelectric random access memory (FeRAM) devices and methods of fabrication2023 11,829,699Method to segregate logic and memory into separate dies for thermal management in a multi-dimensional packaging2023 11,823,725Apparatus and method for endurance of non-volatile memory banks via multi-level wear leveling2023 11,818,897Method of forming a stack of planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell2023 11,817,859Asynchronous circuit with multi-input threshold gate logic and 1-input threshold gate2023 11,817,140Reading scheme for 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line and with individual switches and control on plate-lines of the bit-cell2023 11,816,408Computer-aided design tool for majority or minority inverter graph synthesis2023 11,809,801Computer-aided design tool for circuit logic initialization2023 11,810,608Manganese or scandium doped multi-element non-linear polar material gain memory bit-cell2023 11,800,722Common mode compensation for non-linear polar material based differential memory bit-cell having one transistor and multiple capacitors2023 11,791,233Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging2023 11,792,998Process integration flow for embedded memory with multi-pocket masks for decoupling processing of memory areas from non-memory areas2023 11,790,969Apparatus and method for endurance of non-volatile memory banks via outlier compensation2023 11,792,997Common mode compensation for differential multi-element non-linear polar material based gain memory bit-cell2023 11,790,972Writing scheme for multi-element gain ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches and control on the plate-lines of the bit-cell2023 11,785,782Embedded memory with encapsulation layer adjacent to a memory stack2023 11,784,1643D stacked compute and memory with copper-to-copper hybrid bond2023 11,777,504Non-linear polar material based latch2023 11,770,936Stack of planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell2023 11,769,790Rapid thermal annealing (RTA) methodologies for integration of perovskite-material based trench capacitors2023 11,769,543Writing scheme for 1TNC ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches and control on the plate-lines of the bit-cell2023 11,765,908Memory device fabrication through wafer bonding2023 11,765,909Process integration flow for embedded memory enabled by decoupling processing of a memory area from a non-memory area2023 11,764,1903D stacked compute and memory with copper pillars2023 11,764,790Majority logic gate having paraelectric input capacitors coupled to a conditioning scheme2023 11,757,452OR-and-invert logic based on a mix of majority or minority logic gate with non-linear input capacitors and other logic gates2023 11,758,708Stack of non-planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell2023 11,758,738Integration of ferroelectric memory devices with transistors2023 11,750,197AND-OR-invert logic based on a mix of majority OR minority logic gate with non-linear input capacitors and other logic gates2023 11,751,404FinFET transistor based resistive random access memory2023 11,748,537Computer-aided design tool for logic synthesis of a mix of CMOS gates and majority and minority logic circuits2023 11,751,403Common mode compensation for 2T1C non-linear polar material based memory bit-cell2023 11,741,428Iterative monetization of process development of non-linear polar material and devices2023 11,742,860Fabrication of a majority logic gate having non-linear input capacitors2023 11,737,283Method of forming a stack of non-planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell2023 11,735,245Read scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects2023 11,729,995Common mode compensation for non-linear polar material 1TnC memory bit-cell2023 11,727,260Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits2023 11,729,991Common mode compensation for non-linear polar material based differential memory bit-cell2023 11,721,690Method of adjusting threshold of a ferroelectric capacitive-input circuit2023 11,716,084Pull-up and pull-down networks controlled asynchronously by majority gate or minority gate logic2023 11,716,085Pull-up and pull-down networks controlled asynchronously by threshold gate logic2023 11,716,083Asynchronous circuit with threshold logic2023 11,716,086Asynchronous circuit with majority gate or minority gate logic and 1-input threshold gate2023 11,711,083Majority gate based low power ferroelectric based adder with reset mechanism2023 11,705,906Majority logic gate having ferroelectric input capacitors and a pulsing scheme coupled to a conditioning logic2023 11,705,905Multi-function ferroelectric threshold gate with input based adaptive threshold2023 11,699,699Multi-function threshold gate with adaptive threshold and stacked planar ferroelectric capacitors2023 11,694,9403D stack of accelerator die and multi-core processor die2023 11,694,737Write scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to word-line to minimize write disturb effects2023 11,696,451Common mode compensation for non-linear polar material based 1T1C memory bit-cell2023 11,696,450Common mode compensation for multi-element non-linear polar material based gain memory bit-cell2023 11,688,733Method of adjusting threshold of a paraelectric capacitive-input circuit2023 11,670,352Apparatus and method for endurance of non-volatile memory banks via wear leveling and outlier compensation2023 11,664,371Multi-function threshold gate with adaptive threshold and stacked planar paraelectric capacitors2023 11,664,060Writing scheme for multi-element gain ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell2023 11,664,370Multi-function paraelectric threshold gate with input based adaptive threshold2023 11,658,664Asynchronous circuit with majority gate or minority gate logic2023 11,652,482Parallel pull-up and pull-down networks controlled asynchronously by threshold logic gate2023 11,652,487Parallel pull-up and pull-down networks controlled asynchronously by majority gate or minority gate logic2023 11,646,071Reading scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to bit-line and with individual switches and control on plate-lines of the bit-cell2023 11,641,205Reset mechanism for a chain of majority or minority gates having paraelectric material2023 11,641,747Integration of a ferroelectric memory device with a transistor2023 11,637,090Method of forming a 3D stacked compute and memory2023 11,616,507Ferroelectric based latch2023 11,610,619Pulsing scheme for a 1TNC ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects2023 11,610,620Pulsing scheme for a 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line to minimize read or write disturb effects2023 11,611,345NAND based sequential circuit with ferroelectric or paraelectric material2023 11,605,413Reading scheme for multi-element gain ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell2023 11,605,411Method of forming stacked ferroelectric planar capacitors in a memory bit-cell2023 11,545,204Non-linear polar material based memory bit-cell with multi-level storage by applying different voltage levels2023 11,545,979Compare logic based sequential circuit with ferroelectric or paraelectric material2023 11,538,514Writing scheme for 1TnC ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell2022 11,539,368Majority logic gate with input paraelectric capacitors2022 11,532,635High-density low voltage multi-element ferroelectric gain memory bit-cell with pillar capacitors2022 11,532,342Non-linear polar material based differential multi-memory element bit-cell2022 11,532,344Reading scheme for 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line and with individual switches on plate-lines of the bit-cell2022 11,527,278Non-linear polar material based memory bit-cell with multi-level storage by applying different time pulse widths2022 11,527,277High-density low voltage ferroelectric memory bit-cell2022 11,521,667Stacked ferroelectric planar capacitors in a memory bit-cell2022 11,521,9533D stacked ferroelectric compute and memory2022 11,522,044Ferroelectric capacitor integrated with logic2022 11,521,668Pulsing scheme for a ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects2022 11,521,666High-density low voltage multi-element ferroelectric gain memory bit-cell with planar capacitors2022 11,514,967Non-linear polar material based differential multi-memory element gain bit-cell2022 11,514,966Non-linear polar material based multi-memory element bit-cell with multi-level storage2022 11,509,308Sequential circuit without feedback or memory element2022 11,502,696In-memory analog neural cache2022 11,501,813Method of forming stacked ferroelectric non- planar capacitors in a memory bit-cell2022 11,502,691Method for using and forming low power ferroelectric based majority logic gate adder2022 11,482,528Pillar capacitor and method of fabricating such2022 11,482,270Pulsing scheme for a ferroelectric memory bit-cell to minimize read or write disturb effect and refresh logic2022 11,482,990Vectored sequential circuit with ferroelectric or paraelectric material2022 11,451,232Majority logic gate based flip-flop with non-linear polar material2022 11,430,861Ferroelectric capacitor and method of patterning such2022 11,423,967Stacked ferroelectric non-planar capacitors in a memory bit-cell2022 11,416,165Low synch dedicated accelerator with in-memory computation capability2022 11,418,197Majority logic gate having paraelectric input capacitors and a local conditioning mechanism2022 11,394,3872-input NAND gate with non-linear input capacitors2022 11,381,244Low power ferroelectric based majority logic gate multiplier2022 11,374,574Linear input and non-linear output threshold logic gate2022 11,373,727Apparatus for improving memory bandwidth through read and restore decoupling2022 11,374,575Majority logic gate with non-linear input capacitors and conditioning logic2022 11,373,728Method for improving memory bandwidth through read and restore decoupling2022 11,366,589Efficient method for improving memory bandwidth through read and restore decoupling using restore buffer2022 11,347,994Weight prefetch for in-memory neural network execution2022 11,303,280Ferroelectric or paraelectric based sequential circuit2022 11,295,796Apparatus and method for endurance of non-volatile memory banks via wear leveling and random swap injection2022 11,296,708Low power ferroelectric based majority logic gate adder2022 11,294,985Efficient analog in-memory matrix multiplication processor2022 11,290,111Majority logic gate based and-or-invert logic gate with non-linear input capacitors2022 11,289,497Integration method of ferroelectric memory array2022 11,290,112Majority logic gate based XOR logic gate with non-linear input capacitors2022 11,283,453Low power ferroelectric based majority logic gate carry propagate and serial adder2022 11,277,137Majority logic gate with non-linear input capacitors2022 11,165,430Majority logic gate based sequential circuit2021 11,151,046Programmable interface to in-memory cache processor2021 11,152,3433D integrated ultra high-bandwidth multi-stacked memory2021 11,139,270Artificial intelligence processor with three-dimensional stacked memory2021 11,138,499Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits2021

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2021–2026Patents assigned to KEPLER COMPUTING INC (246)· patent assignee history

2021–2023Patents assigned to INTEL CORP (8)· patent assignee history

2021–2026Based in US· patent location history

2023Patents assigned to KEPLER CORPATING INC (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
KEPLER COMPUTING INC	246	2021–2026
INTEL CORP	8	2021–2023
KEPLER CORPATING INC	1	2023

Locations

Location	Patents	Span
US	254	2021–2026