Inventor
Ming-Tzong Yang
Inventor
Hsin Chu, TW
Overview
Patents· 97 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1023%
H10BElectronic memory devices22%
H10DInorganic electric semiconductor devices18%
H01LSemiconductor devices12%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests10%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%
H01PWaveguides1%
H03HImpedance networks, e.g. resonant circuits1%
PatentTitleYear
10,741,469Thermal via arrangement for multi-channel semiconductor device202010,727,202Package structure202010,361,173Semiconductor package assemblies with system-on-chip (SOC) packages201910,332,830Semiconductor package assembly20199,947,624Semiconductor package assembly with through silicon via interconnect20189,899,261'Semiconductor package structure and method for forming the same'20189,870,980'Semiconductor package with through silicon via interconnect'20189,859,192'Semiconductor structure with through-silicon via'20189,786,560'Semiconductor package structure having first and second guard ring regions of different conductivity types and method for forming the same'20179,712,130'Passive device cell and fabrication process thereof'20179,679,842'Semiconductor package assembly'20179,640,489'Seal ring structure with capacitor'20179,607,894'Radio-frequency device package and method for fabricating the same'20179,570,399'Semiconductor package assembly with through silicon via interconnect'20179,548,289'Semiconductor package assemblies with system-on-chip (SOC) packages'20179,543,232'Semiconductor package structure and method for forming the same'20179,524,948'Package structure'20169,425,098'Radio-frequency device package and method for fabricating the same'20169,373,727'Semiconductor diode'20169,269,664'Semiconductor package with through silicon via interconnect and method for fabricating the same'20169,257,392'Semiconductor package with through silicon via interconnect'20169,190,976'Passive device cell and fabrication process thereof'20158,987,851'Radio-frequency device package and method for fabricating the same'20158,921,941'ESD protection device and method for fabricating the same'20148,860,544'Integrated inductor'20148,810,001'Seal ring structure with capacitor'20148,779,591'Bump pad structure'20148,669,619'Semiconductor structure with multi-layer contact etch stop layer structure'20148,587,056'High-voltage metal-oxide-semiconductor device'20138,278,733'Bonding pad structure and integrated circuit chip using such bonding pad structure'20127,932,581'Lateral bipolar junction transistor'20117,897,995'Lateral bipolar junction transistor with reduced base resistance'20117,671,469'SiGe device with SiGe-embedded dummy pattern for alleviating micro-loading effect'20107,169,668'Method of manufacturing a split-gate flash memory device'20076,258,692'Method forming shallow trench isolation'20016,232,215'Method for forming increased density for interconnection metallization'20016,221,731'Process of fabricating buried diffusion junction'20016,020,251'Method of forming buried diffusion junctions in conjunction with shallow-trench isolation structures in a semiconductor device'20005,981,404'Multilayer ONO structure'19995,902,752'Active layer mask with dummy pattern'19995,895,945'Single polysilicon neuron MOSFET'19995,798,298'Method of automatically generating dummy metals for multilevel interconnection'19985,757,083'Drain off-set for pull down transistor for low leakage SRAM\'s'19985,716,884'Process for fabricating a stacked capacitor'19985,712,500'Multiple cell with common bit line contact and method of manufacture thereof'19985,698,349'Sub-resolution phase shift mask'19975,698,458'Multiple well device and process of manufacture'19975,661,047'Method for forming bipolar ROM device'19975,656,840'Single bit erase flash EEPROM'19975,650,657'Protection from short circuits between P and N wells'19975,650,346'Method of forming MOSFET devices with buried bitline capacitors'19975,633,520'Neuron MOSFET with different interpolysilicon oxide'19975,629,220'Method of manufacture of pull down transistor with drain off-set for low leakage SRAM\'s'19975,604,367'Compact EEPROM memory cell having a floating gate transistor with a multilayer gate electrode'19975,591,549'Self aligning fabrication method for sub-resolution phase shift mask'19975,592,011'Single layer thin film transistor static random access memory cell'19975,587,600'Series MOS ROM with tapered oxide side walls'19965,578,857'Double poly high density buried bit line mask ROM'19965,572,056'High density ROM'19965,569,962'Split polysilicon SRAM cell'19965,554,545'Method of forming neuron mosfet with different interpolysilicon oxide thickness'19965,541,876'Memory cell fabricated by floating gate structure'19965,533,634'Quantum chromeless lithography'19965,516,713'Method of making high coupling ratio NAND type flash memory'19965,510,214'Double destruction phase shift mask'19965,496,200'Sealed vacuum electronic devices'19965,488,004'SOI by large angle oxygen implant'19965,482,900'Method for forming a metallurgy system having a dielectric layer that is planar and void free'19965,480,822'Method of manufacture of semiconductor memory device with multiple, orthogonally disposed conductors'19965,478,679'Half-tone self-aligning phase shifting mask'19955,478,678'Double rim phase shifter mask'19955,468,980'Buried bit line DRAM cell'19955,461,251'Symmetric SRAM cell with buried N+ local interconnection line'19955,459,086'Metal via sidewall tilt angle implant for SOG'19955,451,534'Method of making single layer thin film transistor static random access memory cell'19955,449,644'Process for contact hole formation using a sacrificial SOG layer'19955,444,411'Functional MOS transistor with gate-level weighted sum and threshold operations'19955,439,838'Method of thinning for EEPROM tunneling oxide device'19955,438,009'Method of fabrication of MOSFET device with buried bit line'19955,436,186'Process for fabricating a stacked capacitor'19955,436,190'Method for fabricating semiconductor device isolation using double oxide spacers'19955,429,980'Method of forming a stacked capacitor using sidewall spacers and local oxidation'19955,429,971'Method of making single bit erase flash EEPROM'19955,418,176'Process for producing memory devices having narrow buried N+ lines'19955,394,356'Process for forming an FET read only memory device'19955,393,233'Process for fabricating double poly high density buried bit line mask ROM'19955,380,676'Method of manufacturing a high density ROM'19955,380,673'Dram capacitor structure'19955,372,955'Method of making a device with protection from short circuits between P and N wells'19945,366,918'Method for fabricating a split polysilicon SRAM cell'19945,364,808'Method of making a buried bit line DRAM cell'19945,354,704'Symmetric SRAM cell with buried N+ local interconnection line'19945,350,700'Method of fabricating bipolar transistors with buried collector region'19945,318,921'Method for making a high density ROM or EPROM integrated circuit'19945,306,657'Process for forming an FET read only memory device'19945,258,634'Electrically erasable read only memory cell array having elongated control gate in a trench'19935,180,680'Method of fabricating electrically erasable read only memory cell'1993Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1993–2007Patents assigned to UNITED MICROELECTRONICS CORP (61)· patent assignee history
1993–2013Based in Hsinchu, TW· patent location history
1994–1999Based in Hsin Chu, TW· patent location history
1995Based in Hsin-Tien, TW· patent location history
1996Based in both of, TW· patent location history
2010–2020Patents assigned to MEDIATEK INC (33)· patent assignee history
2010–2020Based in Hsinchu County, TW· patent location history
2012–2016Patents assigned to YANG MING-TZONG (8)· patent assignee history
2012–2014Patents assigned to HUANG YU-HUA (3)· patent assignee history
2014–2016Patents assigned to LEE TUNG-HSING (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| UNITED MICROELECTRONICS CORP | 61 | 1993–2007 |
| MEDIATEK INC | 33 | 2010–2020 |
| YANG MING-TZONGself | 8 | 2012–2016 |
| HUANG YU-HUA | 3 | 2012–2014 |
| LEE TUNG-HSING | 3 | 2014–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsin Chu, TW | 33 | 1994–1999 |
| Hsinchu County, TW | 32 | 2010–2020 |
| Hsinchu, TW | 30 | 1993–2013 |
| both of, TW | 1 | 1996 |
| Hsin-Tien, TW | 1 | 1995 |