Inventor
Hans-Joachim Barth
Inventor
Munich, DE
Overview
Patents· 87 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1035%
H10DInorganic electric semiconductor devices12%
H01LSemiconductor devices10%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
G06FElectric digital data processing4%
Y10TTechnical subjects covered by former us classification3%
H10BElectronic memory devices2%
A41DOuterwear1%
A44BButtons, pins, buckles, slide fasteners, or the like1%
H01GCapacitors1%
PatentTitleYear
10,886,680Snap button fastener providing electrical connection202110,394,280Wearable electronic devices and components thereof201910,193,288Snap button fastener providing electrical connection201910,049,932Method of manufacturing of a sidewall opening of an interconnect of a semiconductor device201810,003,028Hybrid carbon-metal interconnect structures20189,921,694'Wearable computing device'20189,904,321'Wearable electronic devices and components thereof'20189,865,146'System and method for accident avoidance during mobile device usage'20189,818,672'Flow diversion devices'20179,793,220'Detection of environmental conditions in a semiconductor chip'20179,786,733'Moisture barrier capacitors in semiconductor components'20179,680,105'Hybrid carbon-metal interconnect structures'20179,627,804'Snap button fastener providing electrical connection'20179,564,400'Methods of forming stacked microelectronic dice embedded in a microelectronic substrate'20179,536,409'System and method for accident avoidance during mobile device usage'20179,515,049'Flexibly-wrapped integrated circuit die'20169,390,973'On-chip RF shields with backside redistribution lines'20169,385,105'Semiconductor devices'20169,373,588'Stacked microelectronic dice embedded in a microelectronic substrate'20169,245,799'Semiconductor device and method of manufacturing thereof'20169,209,136'Hybrid carbon-metal interconnect structures'20159,209,143'Die edge side connection'20159,123,829'Method for producing chip stacks'20159,012,297'Methods of forming moisture barrier capacitors in semiconductor components'20158,999,756'Method and apparatus for semiconductor device fabrication using a reconstituted wafer'20158,952,487'Electronic circuit arrangement'20158,907,480'Chip arrangements'20148,889,548'On-chip RF shields with backside redistribution lines'20148,786,085'Semiconductor structure and method for making same'20148,786,104'Three-dimensional multichip module'20148,772,087'Method and apparatus for semiconductor device fabrication using a reconstituted wafer'20148,759,207'Semiconductor structure and method for making same'20148,748,287'System on a chip with on-chip RF shield'20148,698,275'Electronic circuit arrangement with an electrical fuse'20148,617,929'On-Chip RF shields with front side redistribution lines'20138,598,718'Three-dimensional multichip module'20138,592,987'Semiconductor element comprising a supporting structure and production method'20138,569,820'Capacitor having a plurality of parallel conductive members'20138,536,683'System on a chip with on-chip RF shield'20138,525,347'Method for producing chip stacks, and associated chip stacks'20138,334,202'Device fabricated using an electroplating process'20128,330,274'Semiconductor structure and method for making same'20128,269,341'Cooling structures and methods'20128,247,910'Three-dimensional multichip module'20128,178,953'On-chip RF shields with front side redistribution lines'20128,169,059'On-chip RF shields with through substrate conductors'20128,148,257'Semiconductor structure and method for making same'20128,138,539'Semiconductor devices and methods of manufacture thereof'20128,063,469'On-chip radio frequency shield with interconnect metallization'20117,986,023'Semiconductor device with inductor'20117,986,033'Three-dimensional multichip module'20117,948,064'System on a chip with on-chip RF shield'20117,936,052'On-chip RF shields with backside redistribution lines'20117,915,132'Corresponding capacitor arrangement and method for making the same'20117,879,727'Method of fabricating a semiconductor device including a pattern of line segments'20117,875,977'Barrier layers for conductive features'20117,855,438'Deep via construction for a semiconductor device'20107,843,035'MIM capacitors with catalytic activation layer'20107,816,792'Semiconductor device with conductive interconnect'20107,812,424'Moisture barrier capacitors in semiconductor components'20107,786,584'Through substrate via semiconductor components'20107,777,300'Semiconductor device with capacitor'20107,763,519'Method for fabricating an interconnect arrangement with increased capacitive coupling and associated interconnect arrangement'20107,759,768'Integrated circuit with intergrated capacitor and methods for making same'20107,755,196'Method for production of an integrated circuit bar arrangement, in particular comprising a capacitor assembly, as well as an integrated circuit arrangement'20107,732,898'Electrical fuse and associated methods'20107,635,908'Corresponding capacitor arrangement and method for making the same'20097,615,440'Capacitor and method of manufacturing a capacitor'20097,449,409'Barrier layer for conductive features'20087,440,334'Multi-transistor memory cells'20087,436,016'MIM capacitor with a cap layer over the conductive plates'20087,285,490'Method for the producing an integrated circuit bar arrangement, in particular comprising a capacitor assembly, in addition to an integrated circuit arrangement'20077,268,383'Capacitor and method of manufacturing a capacitor'20077,193,263'Electronic component having an integrated passive electronic component and associated production method'20076,960,835'Stress-relief layer for semiconductor applications'20056,949,442'Methods of forming MIM capacitors'20056,908,841'Support structures for wirebond regions of contact pads over low modulus materials'20056,893,959'Method to form selective cap layers on metal features with narrow spaces'20056,866,943'Bond pad structure comprising tungsten or tungsten compound layer on top of metallization level'20056,844,245'Method of preparing a self-passivating Cu laser fuse'20056,750,129'Process for forming fusible links'20046,730,982'FBEOL process for Cu metallizations free from Al-wirebond pads'20046,693,343'Self-passivating Cu laser fuse'20046,559,042'Process for forming fusible links'20036,515,373'Cu-pad/bonded/Cu-wire with self-passivating Cu-alloys'20036,451,664'Method of making a MIM capacitor with self-passivating plates'20024,766,296'Article checkout counter and system'1988Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1988Based in Fort Lauderdale, FL, US· patent location history
2002–2017Patents assigned to INFINEON TECHNOLOGIES AG (62)· patent assignee history
2002–2021Based in Munich, DE· patent location history
2007–2014Based in München, DE· patent location history
2011–2017Patents assigned to BARTH HANS-JOACHIM (21)· patent assignee history
2012–2014Patents assigned to BEER GOTTFRIED (5)· patent assignee history
2012–2014Patents assigned to POHL JENS (5)· patent assignee history
2015–2021Patents assigned to INTEL CORP (12)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INFINEON TECHNOLOGIES AG | 62 | 2002–2017 |
| BARTH HANS-JOACHIMself | 21 | 2011–2017 |
| INTEL CORP | 12 | 2015–2021 |
| BEER GOTTFRIED | 5 | 2012–2014 |
| POHL JENS | 5 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Munich, DE | 81 | 2002–2021 |
| München, DE | 5 | 2007–2014 |
| Fort Lauderdale, Florida, US | 1 | 1988 |